JPH02246614A - Logic circuit - Google Patents

Abstract

PURPOSE:To reduce the transient base current and to increase the switching speed even in the presence of a parasitic capacitance by constituting an input transistor(TR) with plural TRs of the pre-stage and the post-stage in Darlington connection. CONSTITUTION:The input TR consists of pre-stage TRs Q1, Q8 whose base receives an input signal and whose collectors connect to a collector side of a reference TR Q3 and post-stage TR Q10 in Darlington connection to the pre- stage TRs Q1, Q8 and whose emitter connects to the reference TR Q3 in common. and is provided with a resistor R5 and differential outputs whose phases are inverted to each other are obtained from the post-stage TR Q10 and the collector side of the reference TR Q3. Thus, a large charge/discharge current due to a parasitic capacitor CCE is not required as to the TR Q1 and a transient base current is reduced.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a logic circuit, and aims to provide a logic circuit that reduces transient base current, has high switching speed, and can take advantage of high speed performance. The emitters of at least one input transistor and a reference transistor whose bases are supplied with a reference voltage are commonly connected, and the emitter current of each transistor is switched according to the level relationship between the input signal and the reference voltage, and the emitter current of each transistor is In a logic circuit that obtains differential outputs whose phases are inverted to each other, the input transistor is connected to at least one pre-stage transistor whose base is supplied with an input signal and whose collector is connected to the collector side of a reference transistor; and the pre-stage transistor. The second transistor is Darlington-connected to the second transistor and has its emitter connected in common with the reference transistor, and is configured to obtain differential outputs whose phases are inverted from each other from the collector sides of the second transistor and the reference transistor.

[Industrial application field]

The present invention relates to logic circuits, and more particularly to non-saturated logic circuits.

In general, non-saturated logic circuits have the shortest delay time among digital ICs and always operate in a non-saturated state. They have a structure in which the emitters of transistors are coupled, and the emitter current always switches according to input information. Therefore, current switching type logic circuit (CML-: current)
t mode logic) and CML
An emitter-coupled logic circuit (EC-L: emitter
There is a type called coupled logic.

[Conventional technology]

An example of a conventional non-saturated logic circuit is the one shown in FIG. What is shown in the same figure is an ECL circuit, which includes two human-powered transistors Ql and G2, a transistor Q3 to which a reference voltage V is applied, a constant current source transistor Q4, load resistors RI and Rt, It has a buffer transistor Q and resistors R2 and R4,
Transistors Q1-Q.

The emitters of are commonly connected. The input voltage ■1 is the reference voltage V□, and if it becomes higher, the transistor Q.

is ON, transistor Q3 is OFF, the collector voltage VC+ of transistor Q1 is low, and transistor Q,
The collector voltage Vc3 of becomes high. On the other hand, if it is low, the relationship is reversed, so the emitter current is switched by the base current, and current always flows through one of the transistors. This relationship is shown by the signal waveform shown in FIG.

The collector of the transistor Q3 becomes the NOR terminal, the collector of the transistor Q3 becomes the OR terminal, and the output of the transistor Q5 becomes the OR output. In addition, regarding power supply, V, c=G N G5Vt
--2V,,Vtt"4.5"'5',2V
D is set.

By the way, to perform various logical operations, use E as shown in Figure 4.
Using the CL circuit as a gate, connections are made as shown in FIG. 5, for example. In the same figure, it is 17! l<drive gate, 2a, 2b, . . . 2n are load gates, all of which are constructed of ECL circuits.

The output of the drive gate 1 distributes many signals that spread like a fan to drive the next logic circuit, that is, the load gates 2a to 2n. At this time, the number of connections that can be made using one load gate as a unit load is generally referred to as fan-out.

[Problem to be solved by the invention]

However, in such conventional logic circuits,
There is a problem in that when there are many load gates and the load is heavy, the switching speed becomes slow and the high speed characteristic of the ECL gate cannot be utilized.

That is, when the level of the input signal is about to change, as shown in FIG. 6, which shows the equivalent circuit of the input transistor Q,
Since the base and collector sides have an opposite phase relationship in the NOR output, a small base current transiently becomes a large charge/discharge current and increases due to the Miller effect associated with the so-called parasitic capacitance CCII.

This is largely due to the fact that the potential variation between the base and collector increases twice as much as the input voltage change (for example, when the input voltage attempts to decrease, the collector voltage increases and the potential difference becomes larger). .

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a logic circuit that reduces transient base current, has high switching speed, and can take advantage of high speed performance.

[Means to solve the problem]

In order to achieve the above object, the logic circuit according to the present invention commonly connects the emitters of at least one input transistor whose base is supplied with an input signal and a reference transistor whose base is supplied with a reference voltage, and connects the input signal and the reference voltage. In a logic circuit that switches the emitter current of each transistor according to the level relationship between the transistors and obtains a differential output from each transistor whose phase is inverted, the input transistor is connected to the base of which an input signal is supplied, and the collector of which is connected to the reference transistor. It consists of at least one front-stage transistor connected to the collector side, and a rear-stage transistor connected to the front-stage transistor by Darlington and whose emitter is commonly connected to the reference transistor, and the rear-stage transistor and the reference transistor are connected to each other. Differential outputs with mutually inverted phases are obtained from the collector side.

[Effect]

In the present invention, the input transistor is constituted by a plurality of front-stage and rear-stage transistors connected in a Darlington connection, an input signal is supplied to the front-stage transistor, and the rear-stage transistor becomes one of the differential outputs. When an input signal is supplied to the base of the previous transistor, the collector side of the previous transistor is in phase with the collector side of the reference transistor, so as a result, the potential difference between the base and collector changes the level of the input signal. remains constant regardless of

Therefore, even if there is a parasitic capacitance, the transient base current is reduced and the switching speed is increased.4 [Embodiment] The present invention will be described below with reference to the drawings.

1 to 3 are diagrams showing an embodiment of a logic circuit according to the present invention. FIG. 1 shows an example in which the present invention is applied to an ECL circuit used as a drive gate or a load gate as previously shown in the conventional example. In the explanation of FIG. 1, the same reference numerals are given to the same components as those of the conventional example, and redundant explanation thereof will be omitted.

In Fig. 1, the difference from the conventional example is that the input transistor is connected to the collector side of the reference transistor (hereinafter simply referred to as a transistor) Q, whose base is supplied with a human input signal and whose collector is connected to the collector side of the reference transistor (hereinafter simply referred to as a transistor). ) Ql.

Q2, and a rear-stage transistor (hereinafter simply referred to as a transistor) Ql, which is Darlington-connected to the front-stage transistors Q+ and Qz, and whose emitter is commonly connected to the reference transistor Q. , a resistor R9 is provided, and a subsequent transistor Q
,. The difference is that differential outputs (OR and NOR) whose phases are inverted from each other can be obtained from the collector sides of the transistor Q and the reference transistor Q.

In the above configuration, when the input voltage of transistor Q is about to change from a high level to a low level as shown in FIG. 2, the collector of the preceding transistor Q1 is connected to the collector of the reference transistor Q. Since they are in the same phase, the potential difference between the base and collector of the preceding stage transistor Ql is kept within a certain range with respect to the change in the input level. That is, when the base potential decreases, the collector potential also decreases, and the potential difference does not increase as in the conventional case. Furthermore, since the transistor Ql and the transistor Q10 are Darlington connected, the transistor Qla operates with a slight change in the input voltage v=1. Therefore, transistor Q does not require a large charging/discharging current due to parasitic capacitance ICc regardless of changes in input level, and transient base current can be reduced.

When this ECL circuit is used as a load gate, the input current of the load gate is reduced and the load seen from the drive gate (the size of the load corresponds to the area of the shaded area) as shown in Figure 3. This means that it is possible to reduce the Therefore, the OR output in this case becomes as shown by the broken line in FIG. 2, and the switching speed improves as the load is reduced.

Incidentally, as mentioned above, conventionally the solid line in the figure shows that the heavier the drive load, the longer the delay time τ until switching, and especially if the load is too large, it becomes difficult to drive. It is also possible. In contrast, in this embodiment, the driving load can be appropriately reduced, the switching speed can be increased, and the high speed characteristic of the ECL circuit can be fully utilized.

From the viewpoint of driving load, as shown in Fig. 3 as other waveforms of the conventional example, there is a reduction in switching speed, and in severe cases, it becomes difficult to drive. However, in this embodiment, such a situation can be effectively avoided. is prevented. In practice, the drive load for one load gate was conventionally about 3 ps, but it has been confirmed as experimental data that this embodiment reduces the drive load by half to about 4 ps. Also, resistor R3
Although the current is limited by the insertion of the inverter to achieve even higher speed, the insertion is not necessarily required in the application of the present invention.

Note that the number of front stage transistors is not limited to two, but may be any other number as long as it is one or more.Also, although the above embodiment is an example in which the present invention is applied to an ECL circuit, the present invention also applies to a buffer circuit. Of course, any CML circuit that is omitted can also be applied.

〔Effect of the invention〕

According to the present invention, it is possible to reduce the transient base current and increase the switching speed, thereby ensuring high speed performance.

[Brief explanation of drawings]

1 to 3 are diagrams showing one embodiment of a logic circuit according to the present invention, FIG. 1 is a circuit diagram thereof, FIG. 2 is a timing chart explaining the effect accompanying a change in input voltage, and FIG. Figure 4 is a diagram explaining the input current waveform, Figures 4 to 6 are diagrams showing conventional logic circuits, Figure 4 is the circuit diagram, Figure 5 is a block diagram when the logic circuit is connected, FIG. 6 is an equivalent circuit of the input transistor. ■...Drive gate, 2a-2n...Load gate, Ql, Qt...Previous stage transistor, Q1
0...Late stage transistor, Q,...Reference transistor, Qa, Qs...Transistor, R, -R,...
·····resistance. Ql, Q2: Front stage transistor Qlo: Later stage transistor Q3: Reference transistor Q4. Qs: ) Transistors R1-R5: Resistors Timing chart explaining the action of the embodiment as a result of changes in input voltage Figure 1 Circuit diagram of a conventional logic circuit Figure 1 Diagram explaining the input current waveform of the embodiment Figure 1 Conventional logic Block diagram when the circuit is connected Diagram Equivalent circuit diagram of conventional input transistor

Claims (1)

[Claims] The emitters of at least one input transistor whose base is supplied with an input signal and the emitters of a reference transistor whose base is supplied with a reference voltage are commonly connected, and the emitters of at least one input transistor whose bases are supplied with an input signal and the emitters of a reference transistor whose bases are supplied with a reference voltage are connected in common, and according to the level relationship between the input signal and the reference voltage, In the logic circuit that switches the emitter current of each transistor by using the input transistor to obtain a differential output whose phase is inverted to each other, the input transistor has a base to which an input signal is supplied, and a collector to the collector side of a reference transistor. It is composed of at least one front-stage transistor, and a rear-stage transistor that is Darlington-connected to the front-stage transistor and whose emitter is commonly connected to a reference transistor, and that the phases of the rear-stage transistor and the reference transistor are mutually different from each other from the collector side. A logic circuit characterized in that it obtains an inverted differential output.