JP2830509B2 - Multiplexer circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplexer circuit, and more particularly to a multiplexer circuit using a wired-OR logic of a bipolar transistor in a semiconductor logic circuit.

[0002]

2. Description of the Related Art A conventional multiplexer circuit has a function of switching signals from a plurality of pre-stage buffer circuits and the like and outputting the signals to a next-stage buffer circuit.

FIG. 6 is a circuit diagram of a wired-OR type multiplexer showing an example of the prior art. As shown in FIG. 6, the wired-OR type multiplexer circuit 2A is defined as bipolar transistors Q1 to Q11 supplied to the base based on the output C1 from the preceding buffer circuit 1A that receives the input signals IN1 and IN2 and the switching signal S. And a current source I1. Collector maximum power supply potential VC of transistor Q1
C, and the emitter is commonly connected to the same bipolar transistors Q10 and Q11, and is grounded to the minimum power supply potential GND through the constant current source I1. Such a common emitter becomes the output bus B1, and is connected to the next-stage buffer circuit 3A. This wired-OR type multiplexer circuit 2A is a bipolar transistor Q having a high driving capability.
1, Q10, Q11, the emitter follower circuit is used to operate at a high speed, and the delay time tpd is approximately 0.1 to
It is about 0.2 ns. However, as a prerequisite for operating as a multiplexer, the base potential of the non-selected transistor must be lower than the low level of the selected transistor. Therefore, when the preceding buffer circuit 1A is formed by an ECL circuit, the input signal I
In addition to N1 and IN2, an emitter junction type current switch having a multiplexer switching signal S as a base input is required, and a differential two-phase output cannot be created only with a single-phase output C1.

FIG. 7 is a transfer gate type multiplexer circuit diagram showing another conventional example. As shown in FIG. 7, when the multiplexer switch signal S is not required for the pre-buffer circuit 1, there is no logical restriction on the inputs C1 and C2 to the multiplexer circuit 2A. This multiplexer circuit 2A receives a signal E via an input emitter follower circuit.
1 and E2 are connected to MOS transistors M10 and M12, respectively.
And the drain side is connected to the output buses B1 and B2, and a plurality of similar transfer gates are commonly supplied to the next-stage buffer circuit 3 via the output buses B1 and B2. Connected. The operation of the multiplexer circuit 2A is such that the MOS transistor forming the transfer gate is switched to the switching signal S1.
Then, a conduction state is established using the inverted signal formed via the inverter INV. All non-selected transfer gates are made non-conductive by the switching signal to operate as a multiplexer circuit. Since the multiplexer circuit 2A has no logical restrictions on the pre-buffer circuit 1, a circuit can be freely constructed as required, such as single-phase output or in-phase / out-phase differential output.

[0005]

In the conventional multiplexer circuit described above, a bipolar wired-or high-speed multiplexer circuit cannot be used unless a logic function is added to the preceding-stage buffer circuit. When a phase output type signal is used as an input signal for a multiplexer circuit, the preceding buffer circuit is significantly complicated, power consumption is increased, and circuit design is troublesome. In addition, the transfer gate type multiplexer circuit using the MOS transistor does not require the addition of a new circuit function to the preceding buffer circuit, but the drain diffusion layer capacitance of the non-selected MOS transistor added to the output common bus is reduced. Since the MOS transistor on the selected side is driven by the wiring capacitance, etc.,
There is a disadvantage that the delay time is greatly increased as compared with the bipolar wired-or-type multiplexer.

SUMMARY OF THE INVENTION An object of the present invention is to provide a multiplexer circuit capable of shortening the delay time and facilitating and expanding the logic design.

[0007]

According to the present invention, there is provided a multiplexer circuit comprising: a first bipolar transistor which is supplied based on logic input signals from a plurality of pre-stage buffer circuits and has a collector connected to a power supply; a second bipolar transistor connected to and emitter connected to the emitter of the first bipolar transistor to a common output bus, the emitter of said first bipolar transistor Oyo
And between the bases of the second bipolar transistor
The first MOS transistor and the second bipolar transistor.
A second transistor connected between the base of the
A plurality of emitter follower circuits including a MOS transistor, and a gate of the first and second MOS transistors.
A switching signal is supplied to the first and second MOS transistors.
The plurality of pre-buffer circuits by switching the transistors to the opposite operation states and switchingly connecting the base of the second bipolar transistor to the emitter of the first bipolar transistor or to a lower set potential.
Output any logical input signal to the next buffer circuit
It is configured to select In addition, the multi
The plexer circuit includes an output of the plurality of emitter follower circuits.
Power can be connected to a bus to create a wired-or configuration
Wear. Further, in the multiplexer circuit of the present invention,
The plurality of emitter follower circuits are connected to the first MOS transistor.
A third MOS transistor in parallel or series with the transistor
And the base of the second bipolar transistor.
Switch between the first and second MOS transistors and
And by the third MOS transistor,
Can control the output level with multiple switching signals.
Wear. Further, in the multiplexer circuit of the present invention,
The ground connection of the second MOS transistor is connected to the second MOS transistor.
Low voltage lower than the base potential of the bipolar transistor
It can be configured in place of connection to the compression signal line.

[0008]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a multiplexer circuit diagram showing a first embodiment of the present invention. As shown in FIG. 1, in the present embodiment, input signals IN1 and IN2 at the ECL level are input from an ECL circuit to a pre-stage buffer circuit 1, and outputs C1 and
C2 is input to the multiplexer circuit 2. These outputs C1 and C2 connect the collectors to the maximum power supply potential VCC.
Are connected to the bases of bipolar transistors Q1 and Q3 connected to the same, and the emitters of the transistors Q1 and Q3 are connected to the collectors of similar bipolar transistors Q2 and Q4. The emitters of these transistors Q2 and Q4 are connected to output bus lines B1 and B
2 is connected. These output bus lines B1 and B2 are grounded to the minimum power supply potential GND through the constant current sources I1 and I2. Accordingly, the multiplexer circuit 2 has a wired-or-type multiplexer configuration. Also,
The bases and collectors of the transistors Q2 and Q4 are respectively a p-type MOS transistor M1 and an n-type MOS transistor M2, and a p-type MOS transistor M4 and an n-type MOS
The source and drain terminals of the transistor M5 are connected. The switching signal S1 is input to the gates of the p-type MOS transistors M1 and M4, and the inverted signal formed via the inverter INV for the switching signal S1 is input to the gates of the n-type MOS transistors M2 and M5. Further, an n-type MOS to which a switching signal S1 is inputted as a gate.
Transistors M3 and M6 are arranged with their source and drain terminals connected between the bases of bipolar transistors Q2 and Q4 and GND. A similar bipolar two-stage emitter follower circuit is provided for each of a plurality of preceding-stage buffer circuits 1, and includes a common emitter of bipolar transistors Q5, Q6 and Q7, Q8,.
B2 is connected to the buffer circuit 3 in the next stage.

Next, the operation of the multiplexer circuit will be described. First, when the switching signal S1 is at a low level, the MOS transistors M1, M2 and M4, M5 are turned on and the MOS transistors M3, M6 are turned off, so that the bipolar transistors Q2, Q4 are diode-connected. Therefore, the outputs C1, C of the pre-stage buffer circuit 1
The information is output bus B1, as a potential lowered from 2 by 2Vf which is twice the pn junction forward voltage Vf (approximately 0.8V).
Appears at B2. On the other hand, at this time, in the other similar emitter follower circuit, the switching signal S1 becomes high level, and the base voltages of the bipolar transistors Q5 and Q6 become the GND potential, so that all the bipolar transistors are turned off. Therefore, only the information C1 and C2 from the preceding buffer circuit 1 selected by the switching signal S1 is transmitted to the next buffer circuit 3. Therefore, unlike the conventional wired-OR type multiplexer circuit, wired-OR switching can be performed only by the switching signal S1 irrespective of the logical configuration of the preceding buffer circuit 1.

Next, regarding the operation speed, the first-stage bipolar transistors Q1 and Q3 have a high capacity and supply a base current to the bases of the bipolar transistors Q2 and Q4 via the on-resistances of the MOS transistors M1, M2 and M4 and M5. At the same time, the MOS transistors M3 and M6
And the additional capacitance of the collectors of bipolar transistors Q2 and Q4, and furthermore, bipolar transistor Q
2 and Q4 charge the emitter capacitance of another circuit added to the common output bus lines B1 and B2, and the potential rising speed is determined. Since the base resistances of these bipolar transistors Q2 and Q4 are usually several kilohms, if the on-resistances of MOS transistors M1 and M2 and M4 and M5 are reduced to about the same value or less, the performance of the bipolar transistors can hardly be reduced. Therefore, when the above-described multiplexer circuit 2 is used, high-speed switching of about a normal wired OR can be realized. On the other hand, the speed at the time of potential drop is
It is determined by discharging the additional capacitance of the buses B1 and B2 by the currents of the constant current sources I1 and I2. This value increases with an increase in the number of switching circuits.
Since it is about 4 pF, the current amount of the constant current sources I1 and I2 may be set to a value determined by the input capacitance and the wiring capacitance of the next-stage buffer circuit 3, and hardly depends on the number of switching circuits. Hereinafter, the relationship between the number of switching circuits (m) and the delay time (tpd) will be described.

FIG. 2 is a diagram for explaining the delay time and signal level of the multiplexer in FIG. 1, and FIG. 3 is a characteristic diagram of the delay time with respect to the number of multiplexes in FIG. As shown in FIG. 2, here, the signal levels on the input side and the output side of the multiplexer circuit 2 are set to be the same, and the delay time is measured. FIG.
As shown in (1), the characteristic (b) of the conventional example is for the multiplexer circuit 2A shown in the figure using a MOS transfer gate, and the former buffer circuit 1, the next buffer circuit 3, and the other wiring capacitance systems are all the same. Compared. As shown in the characteristic (a) of the present embodiment in FIG. 3, the difference becomes remarkable as the multiplex number m increases. For example, in the case of switching of 16 circuits, the delay speed is about 1/5 as shown in the characteristic (a) in the example of FIG. 1 of the present embodiment and the delay time tpd is greatly reduced as compared with the conventional example (b). I do.

FIG. 4 shows a multiplexer circuit according to a second embodiment of the present invention. As shown in FIG.
In the bipolar transistors Q1 and Q2 having a stage configuration,
First transistor Q1 receiving input signal C1 at its base
And a second connecting the emitter to the output bus B1.
For the changeover switch between the bases of the transistors Q2
Only the p-type MOS M1 is used for the S transistor, and the common reference potential VR is used for the source terminal of the MOS transistor M3 for lowering the base potential. If the respective gate voltages VGP (for p-channel) and VGN (for n-channel) in the ON state of these MOS transistors M1 and M3 can be sufficiently obtained, the constituent elements will have the same performance as that of the first embodiment described above. The number can be significantly reduced. Here, assuming that the amplitudes of the input signals C1 and C2 are △ V, the gate voltages VGP and VGN of the MOS are given by the following (1),
It is expressed by equation (2).

VGP = VCC− △ V−Vf (1) VGN = VCC−VR (2) However, the lower limit of the common reference potential VR depends on the reverse base-emitter breakdown voltage VB of the bipolar transistor. Further, since the upper limit depends on the emitter terminal level of the bipolar transistor Q1, VR is within the setting range of the following equation (3).

VCC-2Vf-VB≤VR≤VCC- △ V- △ Vf (3) Accordingly, the gate voltage VGN is represented by the following equation (4).

2Vf + VB ≧ VGN ≧ ΔV + Vf (4) From the above equations (1) and (4), ΔV is as small as about the ECL level (about 1 V or less), and VB is about the normal level (about 3 V or more). If VCC = 5V, then
Since the gate voltages VGP and VGN of the MOS can be 3 to 4 V or more, this embodiment can be realized.

FIG. 5 is a multiplexer circuit diagram showing a third embodiment of the present invention. As shown in FIG. 5, this embodiment shows one emitter follower section in the wired-OR type multiplexer circuit 2. A first bipolar transistor Q1 for inputting an input signal C1 from a preceding buffer circuit (not shown) to a base and a second bipolar transistor Q2 for connecting an emitter to a common output bus line B1
Is the same as the first and second embodiments described above,
This embodiment differs from the other embodiments in that a logic function is added to the base level switching circuit of the transistor Q2. That is, p-type MOS transistors M1A and M1B are connected in series between the emitter of transistor Q1 and the base of transistor Q2, and n-type MOS transistors M1A and M1B are connected between the base of transistor Q2 and VR.
OS transistors M3A and M3B are connected in parallel.
These MOS transistors M1A, M3A and M1
Switching signals S1A and S1B are input to the gates of B and M3B, respectively. These switching signals S1A, S
Only when both 1B become low level, the path of the emitter follower section is selected, and the switching of the multiplexer circuit 2 and the NOR logic function of the switching signal are realized at the same time.

Accordingly, since the delay time required in the conventional logic circuit for generating the switching signal of the multiplexer circuit is eliminated, the switching speed can be increased. Here, it is apparent that other logic designs such as NAND logic can be easily realized by changing the configuration of the CMOS switch circuit that switches the base connection of the transistor Q2.

[0019]

As described above, the multiplexer circuit of the present invention comprises a first transistor receiving an input signal based on a bipolar transistor of a wired-OR type emitter follower circuit, and a collector connected to the emitter of the first transistor. , And a second transistor having an emitter connected to a common output bus line.
By switching the base of the transistor to the emitter of the first transistor or the low potential for non-selection by the switch circuit and performing switching selection of the multiplexer, the high speed of the emitter follower can be achieved without adding a logical configuration or restriction to the preceding buffer circuit. The operation is realized, and it is 1/2 to 1/1 / compared to the transfer gate method using the conventional MOS transistor.
There is an effect that a delay time of about 5 can be realized. Further, since the present invention can incorporate a logic gate of a switch circuit CMOS circuit, there is an effect that an application range of a logic design can be expanded and a higher switching speed can be realized.

[Brief description of the drawings]

FIG. 1 is a multiplexer circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram for explaining a multiplexer delay time and a signal level in FIG. 1;

FIG. 3 is a diagram illustrating delay time characteristics with respect to the number of multiplexes in FIG. 2;

FIG. 4 is a multiplexer circuit diagram showing a second embodiment of the present invention.

FIG. 5 is a multiplexer circuit diagram showing a third embodiment of the present invention.

FIG. 6 is a wired-or-type multiplexer circuit showing an example of the related art.

FIG. 7 is a transfer gate type multiplexer circuit diagram showing another example of the related art.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Pre-stage buffer circuit 2 Multiplexer circuit 3 Sub-stage buffer circuit IN1, IN2 input OUT output Q1-Q8 Bipolar transistor M1-M6 MOS transistor INV Inverter I1, I2 Constant current source B1, B2 Bus S1, S1A, S1B, S2, S3 Switching signal

Claims (4)

(57) [Claims] A first bipolar transistor which is supplied based on logic input signals from a plurality of preceding buffer circuits and has a collector connected to a power supply; and a collector connected to the first bipolar transistor.
A second bipolar transistor having an emitter connected to the emitter of the first bipolar transistor and an emitter connected to the common output bus, and an emitter of the first bipolar transistor.
Between the first bipolar transistor and the base of the second bipolar transistor.
A first MOS transistor connected to the
Connected between the base of the bipolar transistor and ground
A plurality of emitter follower circuits including a second MOS transistor and the first and second MOS transistors
A switching signal is supplied to the gates of the first and second MOS transistors.
The second transistor in the opposite operation state, and the second
By the base of the bipolar transistor for switching and connected to the emitter or low set potential than that of said first bipolar transistor, said plurality of front stage buffer
Output any logical input signal of the buffer circuit to the next buffer circuit.
A multiplexer circuit for selecting whether or not to apply . 2. The multiplexer circuit according to claim 1, wherein said multiplexer circuit has a wired-OR configuration by connecting buses of outputs of said plurality of emitter follower circuits. Wherein said plurality of emitter follower circuit, before
The third MOS transistor is connected in parallel or in series with the third MOS transistor.
MOS transistors are connected, and the base terminal of the second bipolar transistor is switched by the first and second MOS transistors.
2. The multiplexer circuit according to claim 1, wherein the output level is controlled by one or a plurality of switching signals performed by an S transistor and the third MOS transistor . (4) Ground point of the second MOS transistor
The connection is made to the base voltage of the second bipolar transistor.
The connection has been changed to a low-voltage signal line lower than
Claim 1 or Claim 2 or Claim 3
Multiplexer circuit.