JPH04360311A - Multiplexer circuit - Google Patents

Abstract

PURPOSE:To realize the high switching speed by realizing the high speed operation of a degree of an emitter follower without addition or limit of logic constitution to a pre-stage buffer circuit so as to reduce a delay time and so as to extend the application range in the logic design. CONSTITUTION:An emitter follower circuit is formed with a 1st bipolar transistor(TR) Q1 whose base receives a logic input signal C1 and whose collector connects to a power supply VCC and a 2nd bipolar TR Q2 whose collector connects to the emitter of the TR Q1 and whose emitter is connected to a common output bus B1. The a base of the TR Q2 is formed to be switched to a level of the emitter of the TR Q1 or a setting potential GND lower than the level of the emitter.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to multiplexer circuits, and more particularly to multiplexer circuits using wired-OR logic of bipolar transistors in semiconductor logic circuits.

0002

2. Description of the Related Art A conventional multiplexer circuit has a function of switching signals from a plurality of preceding stage buffer circuits and outputting the signals to the next stage buffer circuit.

FIG. 6 is a circuit diagram of a wired-OR type multiplexer showing an example of a conventional multiplexer. As shown in FIG. 6, the wired-OR type multiplexer circuit 2A is defined by bipolar transistors Q1 to Q11 supplied based on the output C1 from the pre-stage buffer circuit 1A which inputs the input signals IN1, IN2 and the switching signal S. It has a current source I1. The collector highest power supply potential VC of this transistor Q1
The emitter is connected to a common emitter of bipolar transistors Q10 and Q11, and is grounded to the lowest power supply potential GND through a constant current source I1. This common emitter becomes an output bus B1 and is connected to the next stage buffer circuit 3A. This wired-OR type multiplexer circuit 2A is a bipolar transistor Q with high driving ability.
Since it uses an emitter follower circuit of 1, Q10, and Q11, it operates at high speed, and the delay time tpd is approximately 0.1 to 0.
．． It is about 2 ns. However, as a necessary condition for operating as a multiplexer, the base potential of the non-selected transistor must be lower than the low level of the selected transistor. Therefore, if the pre-stage buffer circuit 1A is formed of an ECL circuit, the input signal IN
In addition to 1 and IN2, an emitter junction type current switch whose base input is the multiplexer switching signal S is required, and it is not possible to create a differential two-phase output with only the single-phase output C1.

FIG. 7 is a circuit diagram of another conventional transfer gate type multiplexer. As shown in FIG. 7, when the multiplexer switching signal S is not required in the pre-stage buffer circuit 1, there are no logical restrictions on the inputs C1 and C2 to the multiplexer circuit 2A. This multiplexer circuit 2A receives a signal E via an input emitter follower circuit.
1 and E2 are MOS transistors M10 and M12, respectively.
It has a transfer gate configuration in which the power is supplied to the sources of M11 and M13, and the drain side is connected to output buses B1 and B2, and multiple similar transfer gates are commonly connected to the next stage buffer circuit 3 via output buses B1 and B2. Connected. The operation of the multiplexer circuit 2A is such that the MOS transistors constituting the transfer gate are switched by the switching signal S1.
And the inverted signal formed via the inverter INV is used to bring it into conduction. All unselected transfer gates are rendered non-conductive by a switching signal, thereby operating as a multiplexer circuit. Since such a multiplexer circuit 2A has no logical restrictions on the pre-stage buffer circuit 1, the circuit can be freely constructed as required, such as a single-phase output or a differential output of in-phase and anti-phase.

[0005]

[Problems to be Solved by the Invention] In the conventional multiplexer circuit described above, a bipolar wired-OR type high-speed multiplexer circuit cannot be used unless a logic function is added to the front-stage buffer circuit. When a phase output type signal is used as an input signal to a multiplexer circuit, there are disadvantages in that the pre-stage buffer circuit is significantly complicated, power consumption increases, and circuit design becomes troublesome. In addition, although a transfer gate type multiplexer circuit that uses MOS transistors does not require the addition of new circuit functions to the front-stage buffer circuit, it also reduces the drain diffusion layer capacitance of the non-selected MOS transistors added to the output common bus. Since the MOS transistor on the selection side is driven by the wiring capacitance, etc.
The disadvantage is that the delay time is significantly increased compared to a bipolar wired-OR multiplexer.

An object of the present invention is to provide a multiplexer circuit that can shorten such delay time and facilitate and expand logic design.

[0007]

Means for Solving the Problems The multiplexer circuit of the present invention includes a first bipolar transistor whose base is supplied with a logic input signal and whose collector is connected to a power supply, and whose collector is connected to the emitter of the first bipolar transistor. and a second bipolar transistor with its emitter connected to a common output bus, the base of the second transistor being switchably connected to the emitter of the first transistor or a set potential lower than that. configured to do so.

[0008]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a multiplexer circuit diagram showing a first embodiment of the present invention. As shown in FIG. 1, in this embodiment, ECL level input signals IN1 and IN2 are input from the ECL circuit to a pre-stage buffer circuit 1, and the outputs C1,
C2 is input to multiplexer circuit 2. These outputs C1 and C2 each have their collectors connected to the highest power supply potential VCC.
The input signal is input to the bases of bipolar transistors Q1 and Q3 connected to the transistors Q1 and Q3, and the emitters of the transistors Q1 and Q3 are connected to the collectors of similar bipolar transistors Q2 and Q4. The emitters of these transistors Q2 and Q4 are connected to common emitter junctions of output bus lines B1 and B, respectively.
Connected to 2. These output bus lines B1 and B2 are grounded to the lowest power supply potential GND through constant current sources I1 and I2. Therefore, the multiplexer circuit 2 has a wired-OR type multiplexer configuration. Also,
The bases and collectors of the transistors Q2 and Q4 are a p-type MOS transistor M1 and an n-type MOS transistor M2, and a p-type MOS transistor M4 and an n-type MOS, respectively.
The source and drain terminals of transistor M5 are connected. A switching signal S1 is input to the gates of these p-type MOS transistors M1 and M4, and a switching signal S1 is input to the gates of these p-type MOS transistors M1 and M4.
An inverted signal formed via an inverter INV with respect to the switching signal S1 is input to the gates of 2 and M5, respectively. Further, n-type MOS transistors M3 and M6 whose gates receive the switching signal S1 are arranged with their source and drain terminals connected between the bases of the bipolar transistors Q2 and Q4 and GND. A similar two-stage bipolar emitter follower circuit is provided for each pre-stage buffer circuit 1, and bipolar transistors Q5, Q6 and Q
7, Q8... common emitter and output bus lines B1, B
2 is connected to the next stage buffer circuit 3.

Next, the operation of such a multiplexer circuit will be explained. First, when the switching signal S1 is at a low level, the MOS transistors M1, M2 and M4, M5 are turned on, and the MOS transistors M3, M6 are turned off, so that the bipolar transistors Q2, Q4 are diode-connected. Therefore, the outputs C1 and C2 of the pre-stage buffer circuit 1
Information is transmitted to the output buses B1 and B as a potential lowered by 2Vf, which is twice the pn junction forward voltage Vf (approximately 0.8V).
Appears in 2. On the other hand, at this time, in other similar emitter follower circuits, the switching signal S1 becomes high level, and the base voltages of the bipolar transistors Q5 and Q6 become the GND potential, so that all such bipolar transistors are turned off. Therefore, only the information C1 and C2 from the previous stage buffer circuit 1 selected by the switching signal S1 is transmitted to the next stage buffer circuit 3. Therefore, unlike the conventional wired-OR type multiplexer circuit, wired-OR switching can be performed using only the switching signal S1, regardless of the logic configuration of the pre-stage buffer circuit 1.

Next, regarding the operating speed, the first-stage bipolar transistors Q1 and Q3 have high performance and supply base current to the bases of the bipolar transistors Q2 and Q4 via the on-resistances of the MOS transistors M1 and M2 and M4 and M5. At the same time, MOS transistors M3 and M6
and charges the additional capacitance of the collectors of bipolar transistors Q2 and Q4, and further charges the additional capacitance of the collectors of bipolar transistors Q2 and Q4.
, Q4 charge the emitter capacitances of other circuits attached to the common output bus lines B1 and B2, the potential rise speed is determined. Since the base resistance of these bipolar transistors Q2 and Q4 is usually several kilohms, if the on-resistance of MOS transistors M1, M2 and M4, M5 is made to be approximately equal to or less than this value, the performance of the bipolar transistors will hardly deteriorate. Therefore, by using the multiplexer circuit 2 described above, high-speed switching comparable to that of a normal wired OR can be realized. On the other hand, the speed at which the potential falls is determined by the discharge of the additional capacitances of the buses B1 and B2 by the currents of the constant current sources I1 and I2. This value increases as the number of switching circuits increases, but the emitter capacitance is typically 0.01 to 0.04
Since it is approximately pF, the current amount of the constant current sources I1 and I2 can be set to a value determined by the input capacitance and wiring capacitance of the next-stage buffer circuit 3, and is almost independent of the number of switching circuits. The relationship between the delay time (tpd) and the number of switching circuits (m) will be explained below.

FIG. 2 is a diagram for explaining the delay time and signal level of the multiplexer in FIG. 1, and FIG. 3 is a characteristic diagram of the delay time with respect to the number of multiplexes in FIG. 2. As shown in FIG. 2, the signal levels on the input and output sides of the multiplexer circuit 2 are made the same and the delay time is measured. Also, Figure 3
As shown in , the characteristics (b) of the conventional example are for the multiplexer circuit 2A shown in the figure using MOS transfer gates, and the pre-stage buffer circuit 1, the next-stage buffer circuit 3, and other wiring capacitance systems are all the same. There is a comparison. As shown in the characteristic (A) of this embodiment in FIG. 3, the difference becomes more significant as the number of multiplexes m increases. For example, in the case of 16 circuit switching, the delay speed is about 1/5 as shown in the characteristic (A) in the example of FIG. 1 of this embodiment compared to the conventional example (B), and the delay time tpd is significantly reduced. do.

FIG. 4 shows a multiplexer circuit showing a second embodiment of the present invention. As shown in FIG. 4, this example has two
In the bipolar transistors Q1 and Q2 in a stage configuration,
A first transistor Q1 that receives an input signal C1 at its base.
and a second emitter connecting the emitter to the output bus B1.
MO for changeover switch between the bases of transistor Q2 of
The reason is that only the p-type MOS M1 is used as the S transistor, and the common reference potential VR is used as the source terminal of the MOS transistor M3 for lowering the base potential. If the on-state gate voltages VGP (for p-channel) and VGN (for n-channel) of these MOS transistors M1 and M3 are sufficient, the performance of the constituent elements is comparable to that of the first embodiment described above. The number can be significantly reduced. Here, if the amplitude of input signals C1 and C2 is △V, then
The gate voltages VGP and VGN of MOS are as follows (1) and (2
) is expressed by the formula.

[0014] VGP=VCC-△V-Vf...(1)V
GN=VCC-VR...(2
) However, the lower limit of the common reference potential VR is the reverse base-emitter breakdown voltage VB of the bipolar transistor.
Since the upper limit depends on the emitter terminal level of the bipolar transistor Q1, VR falls within the setting range of the following equation (3).

VCC-2Vf-VB≦VR≦VCC-△V-△V
f...(3) Therefore, the gate voltage VGN is expressed by the following equation (4).

2Vf+VB≧VGN≧△V+Vf (
4) From equations (1) and (4) above, if △V is as small as the ECL level (approximately 1 V or less) and VB is as large as the normal level (approximately 3 V or more), then VCC = 5 V and the MOS gate Since the voltages VGP and VGN can be 3 to 4 V or more, this embodiment is possible.

FIG. 5 is a multiplexer circuit diagram showing a third embodiment of the present invention. As shown in FIG. 5, this embodiment shows one emitter follower section in the wired-OR multiplexer circuit 2. As shown in FIG. A first bipolar transistor Q1 whose base receives an input signal C1 from a pre-stage buffer circuit (not shown), and a second bipolar transistor Q2 whose emitter is connected to a common output bus line B1.
The configuration of is the same as the first and second embodiments described above, but
This embodiment differs from others in that a logic function is added to the base level switching circuit of transistor Q2. That is, p-type MOS transistors M1A and M1B are connected in series between the emitter of transistor Q1 and the base of transistor Q2, and n-type MOS transistors M1A and M1B are connected in series between the emitter of transistor Q1 and the base of transistor Q2.
OS transistors M3A and M3B are connected in parallel. These MOS transistors M1A, M3A and M1B
, M3B are supplied with switching signals S1A and S, respectively.
1B is input. These switching signals S1A, S1
Only when both signals B become low level, the path of this emitter follower section is selected, thereby realizing the switching of the multiplexer circuit 2 and the NOR logic function of the switching signal at the same time.

[0018] Accordingly, the delay time required in the logic circuit that generates the switching signal of the conventional multiplexer circuit is eliminated, so that the switching speed can be increased. Here, it is clear that other logic designs such as NAND logic can be easily realized by changing the configuration of the CMOS switch circuit that switches the base connection of transistor Q2.

[0019]

As explained above, the multiplexer circuit of the present invention has a first transistor that receives an input signal based on a bipolar transistor of a wired-OR type emitter follower circuit, and a collector connected to the emitter of the first transistor. and a second transistor whose emitter is connected to the common output bus line.
By switching the base of the first transistor to the emitter of the first transistor or a low potential for non-selection using a switch circuit to select the multiplexer, high-speed operation similar to that of an emitter follower can be achieved without adding any logic configuration or restrictions to the pre-stage buffer circuit. The operation is 1/2 to 1/2 compared to the conventional transfer gate method using MOS transistors.
This has the effect of realizing a delay time of about 5. Further, since the present invention can incorporate the logic gates of the switch circuit CMOS circuit, the range of application of logic design can be expanded and the switching speed can be increased.

[Brief explanation of the drawing]

FIG. 1 is a multiplexer circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram for explaining multiplexer delay time and signal level in FIG. 1;

FIG. 3 is a delay time characteristic diagram with respect to the number of multiplexes in FIG. 2;

FIG. 4 is a multiplexer circuit diagram showing a second embodiment of the present invention.

FIG. 5 is a multiplexer circuit diagram showing a third embodiment of the present invention.

FIG. 6 is a circuit diagram of a wired-OR type multiplexer showing an example of the related art.

FIG. 7 is a circuit diagram of a transfer gate type multiplexer showing another conventional example.

[Explanation of symbols]

1 Pre-stage buffer circuit 2 Multiplexer circuit 3 Next-stage buffer circuit IN1, IN2 Input OUT Output Q1-Q8 Bipolar transistor M1-M6
MOS transistor INV Inverter I1, I2 Constant current source B1, B2 Bus

Claims (3)

[Claims] 1. A first bipolar transistor whose base is supplied with a logic input signal and whose collector is connected to a power supply; and a first bipolar transistor whose collector is connected to the emitter of the first bipolar transistor and whose emitter is connected to a common output bus. 2. A multiplexer circuit comprising: an emitter follower circuit including two bipolar transistors, the base of the second transistor being switchably connected to the emitter of the first transistor or a set potential lower than the emitter of the first transistor. 2. The multiplexer circuit according to claim 1, wherein the multiplexer circuit has a wired-OR configuration by connecting a plurality of outputs of the emitter follower circuit. 3. The emitter follower circuit switches the base terminal of the second bipolar transistor using a MOS transistor.
2. The multiplexer circuit according to claim 1, wherein the multiplexer circuit is implemented by a logic circuit using transistors, and the output level is controlled by one or more switching signals.