JPH04364607A - Emitter coupled logic circuit device - Google Patents

Abstract

PURPOSE:To reduce an output impedance equivalently by supplying a charge current of a load capacitance added to an output terminal from a conductive PNP transistor(TR). CONSTITUTION:PNP TRs Q9, Q8 are connected in parallel with output emitter follower TRs Q4, Q5. Collectors of the TRs Q9, Q8 are connected respectively to NOR output terminals 01, 02. The changeover of the nonconductive and conductive state of the TRs Q9, Q8 is implemented depending on the high and low node potential to which a base is connected, the collector of the TR Q9 or Q8 in the nonconductive state is connected to a terminal from which a logic level VL is outputted and the collector of the TRs Q9 or Q8 in the conductive state is connected to a terminal from which a high logic level VH is outputted. As a result, no adverse effect is almost given onto the output impedance and the current to charge the load capacitance added to the output terminal is almost supplied from the TR Q9 or Q8. Thus, the output impedance is equivalently reduced and the power consumption is not increased.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-speed emitter-coupled logic circuit device with reduced power consumption.

0002

[Prior Art] An emitter-coupled logic circuit (ECL) is a current mode logic circuit that operates a bipolar transistor in a non-saturated manner. Because of its large degree of functional freedom, it is widely used in systems that require high-speed operation, such as general-purpose computers and optical transmission-related digital communications. However, due to the circuit configuration, current always flows through the emitter follower circuit that takes out the logic output, so there is a drawback that the power consumption of the circuit is large. Particularly for integrated circuits, this is a major hindrance to higher integration, and also causes an increase in packaging costs due to the need for heat dissipation.

[0003] Several inventions have been made to solve these problems. Figure 5(a),(b)
These are circuit diagrams showing conventional emitter-coupled logic circuit devices disclosed in, for example, Japanese Patent Application Laid-Open No. 59-115619 and Japanese Patent Application Laid-open No. 59-214327, respectively. Figure 5
In (a), Q1 and Q2 are input transistors whose bases are connected to input terminals I1 and I2, and Q3
is a reference transistor whose base is connected to the reference potential VBB, and R1 is the input transistor Q1, Q2.
A first load resistor, R2, commonly connected to the collectors of
is the second load resistor connected to the collector of the reference transistor Q3, and CS1 has one end connected to the transistor Q1.
, Q2 and Q3 are connected in common, and the other end is connected to the second emitter side power supply VEE1. Q4 is a first current source for supplying a constant current, and the base of Q4 is connected to the input transistors Q1 and Q2. This is an output emitter follower transistor connected to the collector, and the emitter is connected to the NOR output terminal O1. Q6 and Z are a transistor and an impedance element provided for emitter follower current control, respectively. The collector of Q6 is connected to the NOR output terminal O1 together with the emitter of the emitter follower transistor Q4, and the base is connected to the input transistors Q1, Q2 and the reference transistor. It is connected to a connection point 1 between each emitter of Q3 and the first current source CS1, the emitter is connected to an impedance element Z, and the other end of Z is connected to a second emitter side power supply VEE2.

[0004] Also, in FIG. 5(b), Q1, Q
2 is an input transistor whose bases are connected to the input terminals I1 and I2, respectively, Q3 is a reference transistor whose base is connected to the first reference potential VBB1, and R1 is the first power supply VCC and the input transistor Q1.
, Q2, R2 is a second load resistor connected between the first power supply VCC and the collector of reference transistor Q3, and CS1 has one end connected to the input transistor Q1, A first current source for supplying a switching current, Q2 and a reference transistor Q3, each of whose emitters are connected in common, and whose other end is connected to a second emitter-side power supply VEE1;
4 and Q5 have their bases connected to the input transistor Q
The bases of the first and second emitter follower transistors Q6 and Q7 are connected to the collectors of the input transistors Q1 and Q2, the emitters of the reference transistor Q3, and the second reference potential, respectively. VB
B2, and their emitters are connected in common to a second current source CS2 for supplying an emitter follower, and the emitter of the first emitter follower transistor Q4 is The collector of the first emitter follower current switching transistor Q6 is connected to the NOR output terminal O1, and the emitter of the second emitter follower transistor Q5 and the collector of the second emitter follower current switching transistor Q7 are connected to the OR output terminal O2. has been done.

In the above two conventional examples, the emitter side power supply V
Although the case where the EE is separated into the power supply VEE1 of the switching stage and the power supply VEE2 of the emitter follower stage is shown, the two may be connected to give the same potential.

Next, the operation of the circuit shown in FIG. 5(a) will be explained. First, when the input potentials VIN applied to the input terminals I1, I2 are all at a low logic level VL lower than the reference potential VBB, the input transistors Q1,
Q2 becomes non-conductive and reference transistor Q3 becomes conductive. Therefore, the collector potential of the input transistors Q1 and Q2 becomes approximately the VCC potential, and the collector potential of the reference transistor Q3 decreases from the VCC potential by the voltage drop across the load resistor R2. Therefore, according to the base potential of the emitter follower transistor Q4, the NOR output terminal O1 is at a high logic level VH.
becomes. Also, at this time, the input transistors Q1, Q
The potential at point 1, where the emitters of reference transistor Q2 and reference transistor Q3 are commonly connected, becomes a potential VBB-VBE which is lower than reference potential VBB by base-emitter forward voltage VBE of reference transistor Q3.

On the other hand, when the input potential VIN applied to at least one of the input terminals I1 and I2 reaches a high logic level VH higher than the reference potential VBB, the input transistor to which VH is applied becomes conductive. Therefore, the reference transistor Q3 becomes non-conductive. Therefore, the collector potentials of the input transistors Q1 and Q2 are lowered from the VCC potential by the voltage drop across the load resistor R1, and the collector potential of the reference transistor Q3 becomes approximately the VCC potential. Therefore, the NOR output terminal O1 becomes a low logic level VL according to the base potential of the emitter follower transistor Q4. Also at this time,
The potential at point 1, where the emitters of the input transistors Q1, Q2 and the reference transistor Q3 are commonly connected, becomes a potential lower than the high logic level VH by the base-emitter forward voltage VBE of the input transistors, that is, VH -VBE.

As mentioned above, the input transistors Q1 and Q
The potential at point 1, where the emitters of the transistor Q2 and the reference transistor Q3 are commonly connected, that is, the base potential of the transistor Q6 connected to the emitter follower transistor Q4, exhibits a relative high/low change in phase with the change in the input logic level. do. Therefore, by appropriately setting the value of the impedance element Z connected to the emitter of the transistor Q6, the input potential VIN can be lowered to the high logic level V.
When high, transistor Q6 becomes fully conductive,
At a low logic level VL, it can be rendered non-conducting or nearly so.

Next, the operation of the circuit shown in FIG. 5(b) will be explained. First, when the input potentials VIN applied to the input terminals I1, I2 are all at a low logic level VL lower than the reference potential V1, the input transistors Q1,
Q2 becomes non-conductive and reference transistor Q3 becomes conductive. Therefore, the collector potential of the input transistors Q1 and Q2 becomes approximately the VCC potential, and the collector potential of the reference transistor Q3 decreases from the VCC potential by the voltage drop across the load resistor R2. Therefore, emitter follower transistors Q4 and Q
According to the base potential of 5, the output terminal O1 becomes a high logic level VH and the output terminal O2 becomes a low logic level VL. At this time, the potential at point 1, where the emitters of the input transistors Q1, Q2 and the reference transistor Q3 are commonly connected, varies from the reference potential VBB1 to the base-emitter forward direction VBE of the reference transistor Q3.
The potential becomes VBB1 -VBE, which is lowered by the same amount.

On the other hand, when the input potential VIN applied to at least one of the input terminals I1 and I2 reaches a high logic level VH higher than the reference potential VBB1, the input transistor to which VH is applied becomes conductive. Therefore, the reference transistor Q3 becomes non-conductive. Therefore, the collector potentials of the input transistors Q1 and Q2 are lowered from the VCC potential by the voltage drop across the load resistor R1, and the collector potential of the reference transistor Q3 becomes approximately the VCC potential. Therefore, according to the base potentials of the emitter follower transistors Q4 and Q5, the output terminal O1 becomes a low logic level VL and the output terminal O2 becomes a high logic level VH. Also, at this time, input transistors Q1, Q2 and reference transistor Q3
The potential at point 1, where each emitter of is connected in common, is a potential lowered from the high logic level VH by the base-emitter forward voltage VBE of the input transistor, that is, VH - VB.
It becomes E.

As mentioned above, the input transistors Q1, Q
The potential at point 1, where the emitters of the transistor Q2 and the reference transistor Q3 are commonly connected, that is, the base potential of the transistor Q6 connected to the emitter follower transistor Q4, is in phase with the change in the input logic level and has a relatively high or low level. Make a change. Therefore, the value of the reference potential VBB2 applied to the base of the transistor Q7 connected to the emitter follower transistor Q5 is appropriately set (approximately (
VH +VBB1)/2-VBE), when the input potential VIN is at a high logic level VH, the transistor Q6 is turned on and the transistor Q7 is turned off, and when the input potential VIN is at a low logic level VL, the transistor Q6 is turned off and the transistor Q7 is turned off. Q7 can be made conductive.

The above embodiment has the following features for reducing power consumption. That is, according to the circuit configuration of FIG. 5(a), the emitter of the emitter follower transistor Q4, that is, the NOR output terminal O1 is at the high logic level VH.
When , the emitter follower current does not flow much because the transistor Q6 is in a non-conducting state or close to it.
When the emitter of the emitter follower transistor Q4 is at the low logic level VL, the emitter follower current flows because the transistor Q6 is fully conductive.

Furthermore, in the circuit configuration of FIG. 5(b), when the input transistors Q1 and Q2 are all non-conducting, the emitter follower transistor Q4 having a NOR output (at this time at a high logic level VH) has a Since transistor Q6 is in a non-conducting state, almost no current flows, and the OR output (low logic level VL at this time)
) with an emitter follower transistor Q5
Current flows through transistor Q7. Furthermore, when at least one of the input transistors Q1 and Q2 is in a conductive state, a current flows through the transistor Q6 which is in a conductive state to an emitter follower transistor Q4 having a NOR output (which is at a low logic level VL at this time), and a current flows through the transistor Q6 which is in a conductive state. Output (high logic level VH at this time)
) with an emitter follower transistor Q5
Since transistor Q7 is in a non-conducting state, almost no current flows. In other words, when the emitter of the emitter follower transistor Q4 or Q5 (i.e., output terminal O1 or O2) is at the high logic level VH, almost no emitter follower current flows;
When it is L, an emitter follower current flows.

Therefore, in any of the examples, the circuit current can be reduced compared to a circuit configuration in which an emitter follower current always flows regardless of the output level.

[0015]

[Problems to be Solved by the Invention] However, the conventional ECL circuit has an excellent current reduction function because it has a circuit configuration in which a transistor that controls (switches) the emitter follower current is connected to an emitter follower transistor that takes out the output. However, it had the following problems regarding load driving ability.

That is, when the output potential transitions from a low logic level VL to a high logic level VH, the emitter follower current control (switching) transistor connected to the corresponding output emitter follower transistor changes from a conductive state to a non-conductive state or Transition to a state close to that. As a result, the output emitter follower current decreases, and the output impedance of the emitter follower transistor that outputs the high logic level VH increases, which has the negative effect of increasing the output rise time when the load capacitance of the output terminal is large. Become.

The present invention has been made in order to eliminate the drawbacks of the conventional ones as described above, and is an emitter coupling method that can reduce the output impedance of an emitter follower transistor that outputs a high logic level VH without increasing power consumption. The purpose is to provide a logic circuit device.

[0018]

[Means for Solving the Problems] An emitter-coupled logic circuit device according to the present invention includes at least one input transistor whose base is connected to each input signal terminal and whose collector and emitter are each commonly connected; a reference transistor to which a first reference potential is applied, the emitter of which is coupled to the common emitter of the input transistor;
a first resistive element connected between the collector of the reference transistor and the first power supply, a second resistive element connected between the common emitter and the second resistive element;
a first current source connected between the power supplies; a first output transistor having a base connected to the common collector; a first output transistor having a collector connected to the first power supply; and an emitter connected to the first output terminal; a second output transistor whose collector is connected to the collector of the reference transistor, whose collector is connected to the first power supply and whose emitter is connected to the second output terminal; whose base is connected to the common emitter and whose collector is connected to the first output terminal; a first transistor having an emitter connected to the second power supply via a second current source, a base connected to the second reference potential, a collector connected to the second output terminal, and an emitter connected to the second output terminal; a second transistor connected to the second power supply through a second current source; an emitter connected to the first power supply; a base connected to the base of the first output transistor;
A third transistor whose conductive mechanism is complementary to the first output transistor whose collector is connected to the second output terminal, whose emitter is connected to the first power supply and whose base is connected to the second output terminal. The present invention is characterized in that the base of the transistor is provided with a fourth transistor whose conductive mechanism is complementary to the second output transistor whose collector is connected to the first output terminal.

Further, the emitter-coupled logic circuit device according to the present invention includes at least one input transistor whose base is connected to each input signal terminal and whose collector and emitter are respectively commonly connected, and a first reference at the base. a reference transistor to which a potential is applied and whose emitter is coupled to a common emitter of the input transistor;
a first resistive element connected between the common collector of the input transistor and the first power supply; a second resistive element connected between the collector of the reference transistor and the first power supply; a first current source connected between the emitter and the second power source; an output transistor having a base connected to the common collector, a collector connected to the first power source, and an emitter connected to the output terminal; a first transistor having a common emitter, a collector connected to the output terminal, an emitter connected to the second power supply via a second current source, a base connected to the second reference potential, and a collector connected to the first transistor; a second transistor having an emitter connected to the second power source via the second current source; an emitter connected to the first power source; a base connected to the collector of the reference transistor; The present invention is characterized in that the output transistor connected to the output terminal includes a transistor whose conductive mechanism is complementary to the output transistor.

Further, the emitter-coupled logic circuit device according to the present invention includes at least one input transistor whose base is connected to each input signal terminal and whose collector and emitter are respectively commonly connected, and a first reference at the base. a reference transistor to which a potential is applied and whose emitter is coupled to a common emitter of the input transistor;
a first resistive element connected between the common collector of the input transistor and the first power supply; a second resistive element connected between the collector of the reference transistor and the first power supply; a first current source connected between an emitter and a second power source; an output transistor having a base connected to the collector of the reference transistor, a collector connected to the first power source, and an emitter connected to an output terminal; is connected to the common emitter, the collector is connected to the first power source, and the emitter is connected to the second current source through the second current source.
a first transistor connected to a power source, and a second transistor, the base of which is connected to a second reference potential, the collector to the output terminal, and the emitter connected to the second power source via the second current source. and a transistor whose conductive mechanism is complementary to the output transistor whose emitter is connected to the first power supply, whose base is connected to the common collector of the input transistor, and whose collector is connected to the output terminal. It is characterized by this.

Furthermore, an emitter-coupled logic circuit device according to the present invention includes at least one input transistor whose base is connected to each input signal terminal and whose collector and emitter are commonly connected, and a first input transistor connected to the base.
a reference transistor to which a reference potential of is applied and whose emitter is coupled to a common emitter of the input transistor; a first resistive element connected between the common collector of the input transistor and a first power supply; a second resistive element connected between the collector of the input transistor and the first power source, a first current source connected between the common emitter and the second power source, and a base connected to the common collector of the input transistor. , an output transistor whose collector is connected to the first power supply and whose emitter is connected to the output terminal, whose base is connected to the common emitter, whose collector is connected to the output terminal, and whose emitter is connected to the second current source through the second current source.
The transistor connected to the power supply of the transistor and the output transistor whose emitter is connected to the first power supply, whose base is connected to the collector of the reference transistor, and whose collector is connected to the output terminal are transistors whose conductive mechanisms are complementary to each other. It is characterized by having the following.

[0022]

[Operation] In this invention, a third transistor whose conductive mechanism is complementary to the first output transistor is connected in parallel to the first output transistor whose emitter is connected to the first output terminal. A fourth transistor whose conductive mechanism is complementary to the second output transistor is connected in parallel to the second output transistor whose emitter is connected to the second output terminal; The collectors of each of the fourth transistors are connected to mutually opposite output terminals, and the third and fourth transistors are connected to each other according to the level of the node potential to which their respective bases are connected.
Switching between non-conducting and conducting states, the collector of the third or fourth transistor in the non-conducting state is connected to the emitter (i.e. the output terminal) of the second or first output transistor outputting a low logic level VL; Since the collector of the fourth or third transistor in the conductive state is connected to the emitter of the first or second output transistor that outputs the high logic level VH, the collector of the fourth or third transistor in the non-conductive state Alternatively, since the second or first output transistor to which the collector is connected is in a conductive state, the fourth transistor does not have any adverse effect on the output impedance; Since the collector of transistor 3 is connected to the emitter of the first or second output transistor, which has a high output impedance, most of the current for charging the load capacitance added to the output terminal flows through the fourth or second transistor. The output impedance is equivalently reduced.

Further, in the present invention, a transistor whose conductive mechanism is complementary to the output transistor is connected in parallel with the output transistor whose emitter is connected to the output terminal, and the non-conducting and conductive states of the transistor are connected in parallel. switching is performed according to the level of the node potential to which the base of the transistor is connected, and the collector of the transistor is connected to the emitter (i.e., output terminal) of the output transistor, so the transistor is non-conducting. In this state, the output transistor is in a conductive state, so there is no adverse effect on the output impedance.
On the other hand, when the transistor is conductive, the collector of the transistor is connected to the emitter of the output transistor, which has a high output impedance, so most of the current for charging the load capacitance added to the output terminal comes from this transistor. Therefore, the output impedance is equivalently reduced.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing the circuit configuration of an emitter-coupled logic circuit device according to a first embodiment of the present invention, and particularly shows a logic circuit device having a two-input configuration and a NOR output and an OR output. In the figure, Q1 and Q2 are input transistors whose bases are connected to input terminals I1 and I2, respectively, and Q3 is an input transistor whose base is connected to the first reference potential VBB1.
R1 is a first load resistor connected between the first power supply VCC and the common collector of input transistors Q1 and Q2, and R2 is a reference transistor connected between the first power supply VCC and the collector of the reference transistor Q3. CS1 is a first current source for supplying switching current to which the emitters of input transistors Q1, Q2 and reference transistor Q3 are connected in common, and Q4 and Q5 have bases connected to input transistors. First and second emitter follower transistors, Q6, connected to the collectors of Q1 and Q2 and the collector of the reference transistor Q3.
and Q7 have their bases connected to the input transistor Q1.
, Q2, and the respective emitters of the reference transistor Q3 and the second reference potential VBB2, and the respective emitters are connected to a second current source CS for supplying an emitter follower.
The emitter of the first emitter follower transistor Q4 and the collector of the first emitter follower current switching transistor Q6 are the NOR output terminal. O1, the emitter of the second emitter follower transistor Q5 and the collector of the second follower current switching transistor Q7 are connected to the OR output terminal O2, respectively. The bases of Q8 and Q9 are connected to the base of the first emitter follower transistor Q4 and the base of the second emitter follower transistor Q5, respectively, the emitters are commonly connected to the first power supply, and the collectors are respectively connected to the second output terminal O2. and first and second PNP transistors for reducing output impedance connected to the first output terminal O1, and this embodiment is different from the conventional example.

Next, the operation of the emitter-coupled logic circuit device of this embodiment constructed as described above will be explained. Since the basic logic operation is the same as that of the conventional circuit, it will be omitted, and only the part related to the operation of the output impedance reducing PNP transistor, which is the center of the present invention, will be explained.

When input transistors Q1 and Q2 are all non-conducting, almost no current flows through the emitter follower transistor Q4 having a NOR output (which is now at a high logic level VH) since transistor Q6 is non-conducting. First, current flows through the emitter follower transistor Q5, which has an OR output (now at a low logic level VL), through the transistor Q7. Therefore, the impedance of the output terminal that outputs VH tends to be high. However, the PNP transistor Q9 whose collector is connected to the NOR output has an emitter
Since the base is biased in the forward direction, it becomes conductive, and the load capacitance of the NOR output terminal is charged by the current in the conductive state of Q9. On the other hand, the PNP transistor Q8 whose collector is connected to the OR output is
Since the emitter and base are at substantially the same potential, they are in a non-conducting state, and the charge stored in the load capacitance of the OR output terminal is discharged through transistor Q7 in the same manner as in the operation of the conventional circuit.

Furthermore, when at least one of the input transistors Q1 and Q2 is conductive, current flows through the conductive transistor Q6 to the emitter follower transistor Q4 having a NOR output (at this time at a low logic level VL). Almost no current flows through the emitter follower transistor Q5, which has an OR output (now at a high logic level VH), since transistor Q7 is non-conducting. Therefore, it becomes difficult for the emitter follower transistor Q5 to supply current for charging the load capacitance of the OR output terminal. That is, the impedance of the output terminal that outputs VH tends to increase. However, the PNP transistor Q8 whose collector is connected to the OR output becomes conductive because the emitter and base are forward biased, and the OR output becomes conductive.
The load capacitance at the output terminal will be charged by the current of Q8. On the other hand, at this time, the PNP transistor Q9 whose collector is connected to the NOR output is non-conductive because the emitter and base are at almost the same potential, and the NOR output is non-conductive.
The charge accumulated in the load capacitance of the output terminal is discharged through the transistor Q6 in the same manner as in the operation of the conventional circuit.

As described above, according to the emitter-coupled logic circuit device of this embodiment, the PNP transistors Q9, Q5 are connected in parallel with the output emitter follower transistors Q4, Q5.
Q8 is connected, PNP transistors Q9 and Q8
The collectors of PNP transistors Q9 and Q8 are connected to the NOR output terminal O1 and the OR output terminal O2, respectively.
The collector of the PNP transistor in the non-conducting state is switched between the non-conducting and conducting states according to the level of the node potential to which the respective bases are connected. ) and is in conduction state.
Since the collector of the NP transistor is connected to the emitter that outputs a high logic level VH, the PNP transistor in a non-conducting state will have an output impedance because the emitter follower transistor to which the collector is connected is in a conducting state. has no negative effect; on the other hand,
The collector of the PNP transistor that becomes conductive is connected to the emitter of the emitter-follower transistor, which has a high output impedance, so most of the current for charging the load capacitance added to the output terminal flows through this PNP transistor.
The output impedance of the emitter follower transistor that outputs the high logic level VH can be reduced without increasing power consumption.

[0029] In the above embodiment, the case where both NOR and OR outputs were taken out was explained;
It may be the case that only the output or only the OR output is taken out. In that case, the emitter follower transistor of the unused output is removed, and the collector of the transistor to be connected to the emitter of the emitter follower transistor is connected to the first power supply. The PNP transistor connected to VCC and having its collector connected to an unused output may also be removed, and the effect of reducing the output impedance is the same as in the above embodiment.

That is, FIG. 2 shows the circuit configuration of an emitter-coupled logic circuit device according to a second embodiment of the present invention, which is a circuit configuration of an emitter-coupled logic circuit device according to the first embodiment shown in FIG. The second output transistor Q5 and the second output terminal O2 are removed, and the first PNP transistor Q8 is also removed to use only the NOR output. The operation of this embodiment is exactly the same as the operation related to the NOR output in the first embodiment shown in FIG. 1, so a description thereof will be omitted.

FIG. 3 shows a circuit configuration of an emitter-coupled logic circuit device according to a third embodiment of the present invention, and this embodiment uses the emitter-coupled logic circuit of the first embodiment shown in FIG. The first output transistor Q4 and the first output terminal O1 of the device are removed, and the second PNP transistor Q9 is also removed to use only the OR output. The operation of this embodiment is also exactly the same as the operation regarding the OR output in the first embodiment shown in FIG. 1, so the explanation thereof will be omitted.

In the second and third embodiments as described above, a PNP transistor is connected in parallel with the emitter follower transistor, and the base of the PNP transistor is connected to switch the non-conductive and conductive states of the PNP transistor. Since the collector of the PNP transistor is connected to the emitter (i.e., the output terminal) of the emitter follower transistor according to the level of the node potential, when the PNP transistor is in a non-conducting state, the emitter follower transistor is in a conducting state, and the output impedance changes. On the other hand, when the PNP transistor is conductive, the collector of the transistor is connected to the emitter of the emitter follower transistor, which has a high output impedance, so it charges the load capacitance added to the output terminal. Most of the current is supplied from this transistor, and the output impedance is equivalently reduced, thereby reducing the output impedance of the emitter follower transistor that outputs the high logic level VH without increasing power consumption. be able to.

FIG. 4 shows a circuit configuration of an emitter-coupled logic circuit device according to a fourth embodiment of the present invention. The second transistor Q7 for switching (controlling) the follower current is removed.

Next, the operation of the fourth embodiment will be explained. When input transistors Q1 and Q2 are all non-conductive, transistor Q6 can be made non-conductive or close to non-conductive by appropriately configuring the circuit of the second current source CS2 for supplying emitter follower current. At this time, NOR which is a high logic level VH
Since almost no current flows through the emitter follower transistor Q4 having an output, the output impedance tends to be high. However, the PNP transistor Q9 whose collector is connected to this NOR output becomes conductive because the emitter and base are biased in the forward direction, and the load capacitance of the NOR output terminal is charged by the conduction state current of the PNP transistor Q9. will be done.

Furthermore, when at least one of the input transistors Q1 and Q2 is in a conductive state, the base potential of the transistor Q6 also rises to become conductive. At this time, current flows through the emitter follower transistor Q4, which has a NOR output at a low logic level VL, through the conductive transistor Q6. The PNP transistor Q9, whose collector is connected to the NOR output, is non-conductive because the emitter and base are at almost the same potential, and the NOR output is non-conducting.
The charge stored in the load capacitance of the OR output terminal will be discharged through transistor Q6.

Therefore, in this embodiment, as in the above embodiments, the collector of the PNP transistor Q9 in the conductive state is connected to the emitter of the emitter follower transistor Q4, which has a high output impedance. Most of the current for charging the load capacitance is supplied from the PNP transistor Q9, and as a result, the output impedance of the terminal that outputs a high logic level can be equivalently reduced.

In the above embodiment, the emitter side power supply VEE is separated into the switching stage power supply VEE1 and the emitter follower stage power supply VEE2, but the present invention is not limited to this. , a configuration may be adopted in which both are connected and the same potential is applied.

[0038]

As described above, according to the present invention, a PNP transistor is newly connected in parallel with the output emitter follower transistor, and the collectors of each of the PNP transistors are connected to mutually opposite output terminals.
By switching between non-conducting and conducting states according to the level of the node potential to which each base is connected, the collector of the PNP transistor in the conducting state becomes the emitter of the emitter-follower transistor (which outputs a high logic level VH) with a high output impedance. Since most of the current for charging the load capacitance added to the output terminal is supplied from the PNP transistor, it is possible to connect the terminal to output a high logic level without increasing power consumption. This has the effect that the output impedance can be equivalently reduced.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a circuit configuration of an emitter-coupled logic circuit device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a circuit configuration of an emitter-coupled logic circuit device according to a second embodiment of the present invention.

FIG. 3 is a diagram showing a circuit configuration of an emitter-coupled logic circuit device according to a third embodiment of the present invention.

FIG. 4 is a diagram showing a circuit configuration of an emitter-coupled logic circuit device according to a fourth embodiment of the present invention.

FIG. 5 is a diagram showing a circuit configuration of a conventional emitter-coupled logic circuit device.

[Explanation of symbols]

Q1, Q2 Input transistor Q3
Reference transistor Q4
, Q5 first and second emitter follower transistors (first and second output transistors) CS
1 Current source for switching current supply (first current source) Q6, Q7 Transistor for emitter follower current switching (first, second transistor) CS2 Current source for emitter follower current supply (second current source) Q8, Q9 Output impedance reduction transistor (first and second PNP transistor) I1
, I2 input terminal

Claims (4)

[Claims] 1. At least one input transistor, the base of which is connected to each input signal terminal, the collector and the emitter of which are each commonly connected;
a reference transistor to which a reference potential of is applied and whose emitter is coupled to a common emitter of the input transistor; a first resistive element connected between the common collector of the input transistor and a first power supply; a second resistive element connected between the collector of and the first power source; a first current source connected between the common emitter and the second power source; The emitter is connected to the first power supply.
a first output transistor connected to the output terminal of the
The base is the collector of the above reference transistor,
a second output transistor having a collector connected to the first power supply, an emitter connected to a second output terminal, a base connected to the common emitter, a collector connected to the first output terminal, and an emitter connected to the second output terminal; a first transistor connected to the second power source via a current source; a base connected to the second reference potential; a collector connected to the second output terminal; and an emitter connected to the second power source via the second current source. a second transistor connected to the second power supply; an emitter connected to the first power supply; a base connected to the base of the first output transistor; and a collector connected to the second output terminal. A third transistor whose conductive mechanism is complementary to the first output transistor, whose emitter is connected to the first power supply, whose base is connected to the base of the second output transistor, and whose collector is connected to the first output terminal. An emitter-coupled logic circuit device comprising: a fourth transistor whose conductive mechanism is complementary to the second output transistor connected to the emitter-coupled logic circuit device. 2. At least one input transistor, the base of which is connected to each input signal terminal, the collector and the emitter of which are each commonly connected;
a reference transistor to which a reference potential of is applied and whose emitter is coupled to a common emitter of the input transistor; a first resistive element connected between the common collector of the input transistor and a first power supply; a second resistive element connected between the collector of and the first power source; a first current source connected between the common emitter and the second power source; a base connected to the common collector; an output transistor whose emitter is connected to the output terminal to the first power supply, whose base is connected to the common emitter, whose collector is connected to the output terminal, and whose emitter is connected to the second power supply via a second current source. a first transistor connected, and a second transistor having a base connected to a second reference potential, a collector connected to the first power supply, and an emitter connected to the second power supply via the second current source. The transistor includes a transistor whose conductive mechanism is complementary to the output transistor whose emitter is connected to the first power supply, whose base is connected to the collector of the reference transistor, and whose collector is connected to the output terminal. Emitter-coupled logic circuit device featuring features. 3. At least one input transistor having a base connected to each input signal terminal and having a collector and an emitter connected in common;
a reference transistor to which a reference potential of is applied and whose emitter is coupled to a common emitter of the input transistor; a first resistive element connected between the common collector of the input transistor and a first power supply; a second resistive element connected between the collector of the reference transistor and the first power source, a first current source connected between the common emitter and the second power source, and a base of which is connected to the collector of the reference transistor; The collector is the first
an output transistor whose emitter is connected to the output terminal, a base connected to the common emitter, a collector connected to the first power source, and an emitter connected to the second power source via a second current source. a second transistor having a base connected to a second reference potential, a collector connected to the output terminal, and an emitter connected to the second power supply via the second current source; A transistor having an emitter connected to the first power supply, a base connected to a common collector of the input transistor, and a collector connected to the output terminal, the transistor having a complementary conduction mechanism to the output transistor. emitter-coupled logic circuit device. 4. At least one input transistor, the base of which is connected to each input signal terminal, the collector and the emitter of which are each commonly connected;
a reference transistor to which a reference potential of is applied and whose emitter is coupled to a common emitter of the input transistor; a first resistive element connected between the common collector of the input transistor and a first power supply; a second resistive element connected between the collector of the input transistor and the first power source, a first current source connected between the common emitter and the second power source, and a base connected to the common collector of the input transistor. , an output transistor having a collector connected to the first power supply, an emitter connected to the output terminal, a base connected to the common emitter, a collector connected to the output terminal, and an emitter connected to the second current source through the second current source.
The transistor connected to the power supply of the reference transistor and the output transistor whose emitter is connected to the first power supply, whose base is connected to the collector of the reference transistor, and whose collector is connected to the output terminal are complementary in conduction mechanism. An emitter-coupled logic circuit device comprising: