JPH0613584A - Gate array system integrated circuit and its forming method - Google Patents

Abstract

PURPOSE:To minimize power consumption while securing the value of transmission delay time in a specified signal path by a method wherein the value of current, which flows through the ECL circuit of a cell and an emitter follower output circuit, is changed in accordance with the magnitude of a load applied on the emitter follower output circuit of the driving cell. CONSTITUTION:Emitter resistance elements R1-R3 are arranged between the emitter of a transistor Q1 and a power supply Vcc while pull down resistance elements R10-R12 are arranged between the emitter of a transistor Q4 for emitter follower and a power supply Vtt. The resistance elements are connected selectively through wirings so that the ratio of resistance values of respective resistance element groups becomes constant at all times whereby the value of current, which is conducted through an ECL circuit and an emitter follower output circuit, is changed. By this method, power consumption can be minimized while securing the value of delay time of a specified signal path.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate array type integrated circuit and a method of forming the same, and more particularly to a cell configuration of a gate array type integrated circuit including an ECL circuit.

[0002]

2. Description of the Related Art Conventionally, basic cells or basic logic circuits composed of transistors, diodes, resistance elements, etc. are regularly arranged on a semiconductor substrate, and the basic cells or basic circuits are specified by wiring connection according to the purpose. Gate array type integrated circuits, which are used to obtain integrated circuits of various types, are often used because the number of man-hours and periods required for designing and manufacturing can be significantly saved, and it is possible to stock wafers that have been processed just before the wiring process. ing. And ECL (Emitt
The gate array method is also used in integrated circuits including er coupled logic) circuits.

FIG. 6 shows a cell of a gate array type integrated circuit including a conventional ECL circuit and its layout. Figure 6
, A ′, b ′, c ′, d ′ are cells having the same configuration. In the cell a ′, an ECL circuit is composed of a constant current source composed of the transistor Q1 and the resistance element r1, and a current switching type logic part composed of the transistors Q2 and Q3 and the resistance elements r2 and r3. Connected to terminal 1. Q4 is a transistor for an emitter follower, the base of which is connected to the output terminal 4 of the ECL circuit, the emitter of which is connected to the pull-down resistor element r4, and the output terminal 2 which constitutes an emitter follower output circuit. .

The voltage V _CS is applied to the base of the transistor Q1 and the voltage V _bb is applied to the base of the transistor Q3. Further, the power supply _Vcc is generally a ground voltage. Power supply V _ee , V
_tt is, for example, −4.5V and −2V, respectively, and power for operating this circuit is supplied by this power supply. The cells b ', c', and d'also have the same configuration contents. Several such cells are combined and wired to obtain a desired circuit. For example, in the circuit example shown in FIG. 6, the output terminal 2 of the cell a'is connected to the input terminals 1 of the cells b ', c', d ', and drives the cells b', c ', d'.

[0005]

However, depending on the circuit configuration, it is necessary to drive only the cell b'with the output of the cell a ', or to drive the cells b'-d' with the output of the cell a '. It will come out in some cases. Furthermore, cells b ′ to d
It is also possible to drive the fourth and fifth cells other than '. Even in these cases, since the transistor and the resistance element forming the cell a ′ are the same, the values of the current I _cs flowing through the current switching type logic unit and the current I _ef flowing through the emitter follower output circuit are also unchanged. Therefore, cell a
Cell b'to cell d'for the current value or power of '
As a load, there is a drawback that the speed becomes slower when the number of loads is larger than the power of the drive gate, and an excessive current flows when the load is small, resulting in power loss.

An object of the present invention is to respond to changes in the load on the output side of the ECL circuit of the cell a ', the currents I _cs and I _cs.
An object of the present invention is to provide a gate array type integrated circuit in which power consumption is suppressed to a minimum while securing a value of a propagation delay time required in a specific signal path by changing _ef , and a method of forming the same.

[0007]

A gate array type integrated circuit according to the present invention includes a plurality of cells each having an ECL circuit and an emitter follower output circuit to which an output of the ECL circuit is input. And a plurality of resistance elements selectively wire-connected to change the current value of the emitter follower output circuit into at least two ways.

Here, each of the resistance elements forming the ECL circuit and the emitter follower output circuit is made up of at least two resistance elements in advance as a resistance element group, and the size or demand of the output load attached to the basic cell is required. The resistance elements can be selectively connected by wiring in the resistance element group according to the speed.

Further, in the method for forming a gate array type integrated circuit according to the present invention, the resistance element group is constituted by at least three resistance elements each having a resistance ratio of 1: 2: 4, and these resistance elements are connected. Each resistance element constituting the ECL circuit and the emitter follower output circuit by realizing at least seven kinds of resistance values having a resistance ratio of 1: 2: 3: 4: 5: 6: 7 in each resistance element group by the method. Selectively wire-connect the resistance elements so that the ratio of the resistance values of the group is always constant,
At least seven kinds of current values flowing in the ECL circuit and the emitter follower output circuit are made variable so that the relationship between the propagation delay time between cells and the resistance value of each resistance element group can be estimated in advance. Then, the E
The connection of the resistance element corresponding to the magnitude of the current value of the CL circuit and the emitter follower output circuit is selected.

[0010]

In the gate array type integrated circuit of the present invention, the ECL circuit and the emitter follower output circuit of this cell are connected by a method of connecting a plurality of resistance elements according to the size of the load applied to the emitter follower output circuit of the driving cell. It is possible to minimize the power consumption while changing the value of the current flowing through to secure the value of the propagation delay time of the specific signal path.

[0011]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 shows an embodiment of a cell arrangement of a gate array type integrated circuit of the present invention, and the same symbols as those in FIG. 6 indicate the same parts. Resistance element groups arranged between the emitter of the transistor Q1 and the power source V _ee , between the collectors of the transistors Q2 and Q3 and the power source V _cc , and between the emitter of the transistor Q4 and the power source V _tt have a resistance ratio of 1: respectively. 2: 4 of 3
This is an example in the case of being composed of individual resistance elements.

[0012] emitter resistor element R1-R3 (R between the emitter and the power supply V _ee of the constant current source comprising transistor Q1
1 = Rd, R2 = 2Rd, R3 = 4Rd), and collector resistance elements R are respectively provided between the collectors of the transistors Q2 and Q3 which are current switching type logic units and the power supply _Vcc.
4 to R6 (R4 = Ra, R5 = 2Ra, R6 = 4Ra)
And R7 to R9 (R7 = Rb, R8 = 2Rb, R9 =
4Rb), and pull-down resistance elements R10 to R12 (R10 = Rc, R11 = 2Rc, R1) between the emitter of the transistor Q4 for emitter follower and the power supply V _tt.
2 = 4Rc) is arranged. Each of these resistance elements R1 to R
The resistor elements R1 to R12 are selectively wired and connected so that an appropriate current flows according to a load connected to the output terminal 2. The cell is configured as described above. here,
Ra to Rd are arbitrary, and of course Ra = Rb = Rc = Rb.
In some cases.

When the resistance element group is composed of three resistance elements each having a resistance ratio of 1: 2: 4, the resistance ratio in each resistance element group is 1: 2: 3: 4 depending on the connection method of the resistance elements. :
7 types of resistance values of 5: 6: 7 can be realized, and the resistance elements are selectively wired and connected so that the resistance value ratio of each resistance element group forming the ECL circuit and the emitter follower output circuit is always constant. , The current value flowing in the ECL circuit and the emitter follower output circuit can be varied up to 7 types, and the relationship between the propagation delay time of the ECL circuit with the emitter follower and the resistance value of each resistance element group can be estimated in advance as shown in FIG. It is possible. Then, the magnitude of the total current of the ECL circuit with the emitter follower can be adjusted with reference to the estimation. An example is shown below.

FIG. 3 is a circuit diagram showing a second embodiment in which two cells are arranged. In this embodiment, there are two cells a and b, and the load of the output terminal 2 of the cell a is only the cell b. Therefore, the power of the cell a may be small and the resistance element R
All of 1 to R3, R4 to R6, R7 to R9, and R10 to R12 are connected in series and used. In this case, the resistance value corresponds to 7R in FIG.

FIG. 4 is a circuit diagram of the third embodiment of the present invention. In this embodiment, the number of cells is four and the load of the cell a is three. The contents of cells a to d are the same as in the first embodiment. In the third embodiment, cells b, c and d are connected as the load of the cell a, and the load of the output terminal 2 is heavier than that of the second embodiment.

Therefore, in response to the increase in the output load, the resistance elements R3, R6, R are provided in the cell a, which is a driving cell.
Only 9 and R12 are used. With such a connection, the cell a has a large driving capability and can drive all loads at a sufficiently high speed. In this case, the resistance value corresponds to 4R in FIG.

FIG. 5 is a circuit diagram of the fourth embodiment of the present invention. This embodiment has four cells and is the same as the case of the third embodiment. The fourth embodiment is a case where the signal transmission delay time from the cell a to the cell b needs to be shortened as compared with the third embodiment. Therefore, the resistance elements R1, R4, R7, and R10 are used in the cell a, which is a driving cell. By connecting the resistance element in this way, the third
The cell a has a large driving capability as compared with the third embodiment, and the propagation delay time of the signal from the cell a to the cell b can be shortened as compared with the third embodiment. This corresponds to where the resistance value is R in FIG.

In Embodiments 2 to 4 described above, each resistance element group R1
.About.R3, R4 to R6, R7 to R9, and R10 to R12 are shown as three connection methods, other connection methods are possible and even if the number of resistance elements forming this resistance element group is three or more. It goes without saying that the same idea applies. Further, although the characteristics of the transistors are all the same here, if the characteristics of the transistor change, the resistance element may be selected according to the change.

In the above description, the gate array is EC
Although the case where it is configured by the L circuit has been described, the present invention is NTL (N
It goes without saying that the invention can be applied to a gate array type integrated circuit including a basic cell such as an on threshold logic circuit.

[0020]

As described above, the present invention includes a plurality of cells each having an ECL circuit and an emitter follower output circuit to which the output of the ECL circuit is input, and the current values of the ECL circuit and the emitter follower output circuit are included. Since a plurality of resistance elements that are selectively wire-connected in order to change at least two ways are provided, the value of the current flowing through the ECL circuit and the emitter follower output circuit depends on the connection method of the plurality of resistance elements and the size and demand of the output load. There is an effect that the power consumption can be minimized while the value of the delay time of the specific signal path is ensured by changing the signal according to the propagation delay time of the signal.

In addition, the one composed of at least three resistance elements having a resistance ratio of 1: 2: 4 has at least seven kinds of resistance ratios of 1: 2: 3: 4: 5: 6: 7 depending on the connection method. A resistance value can be realized.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a cell configuration of an embodiment of a gate array type integrated circuit of the present invention.

FIG. 2 is a diagram showing a relationship between a resistance value of a resistance element forming an ECL circuit and an emitter follower output circuit and a propagation delay time.

FIG. 3 is a circuit diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a third exemplary embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a fourth exemplary embodiment of the present invention.

FIG. 6 is a circuit diagram showing a configuration of an example of a conventional gate array type integrated circuit.

[Explanation of symbols]

 1 input terminal 2 output terminal a cell b cell c cell d cell Q1 transistor Q2 transistor Q3 transistor Q4 transistor R1 emitter resistance element R2 emitter resistance element R3 emitter resistance element R4 collector resistance element R5 collector resistance element R6 collector resistance element R7 collector resistance element R8 collector resistance element R9 collector resistance element R10 pull-down resistance element R11 pull-down resistance element R12 pull-down resistance element

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Yuichiro Takei 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Corporation

Claims (3)

[Claims] 1. A plurality of cells each having an ECL circuit and an emitter follower output circuit to which the output of the ECL circuit is inputted, for changing the current values of the ECL circuit and the emitter follower output circuit into at least two ways. A gate array type integrated circuit comprising a plurality of resistance elements selectively connected by wiring. 2. The gate array type integrated circuit according to claim 1, wherein each resistance element in the ECL circuit and the emitter follower output circuit is made up of at least two resistance elements in advance, and is attached to the cell. A gate array type integrated circuit characterized in that the resistance elements can be selectively connected in wiring within the resistance element group according to the size of the output load or the required speed. 3. The method of forming a gate array integrated circuit according to claim 2, wherein the resistance element group is composed of at least three resistance elements each having a resistance ratio of 1: 2: 4. Each resistance element that realizes at least seven types of resistance values having a resistance ratio of 1: 2: 3: 4: 5: 6: 7 in each resistance element group by the connection method of 1 and constitutes an ECL circuit and an emitter follower output circuit. The resistance elements are selectively wired and connected so that the ratio of the resistance values of the groups is always constant,
At least seven kinds of current values flowing in the circuit and the emitter follower output circuit are made variable, and the relationship between the propagation delay time between cells and the resistance value of each resistance element group can be estimated in advance. A method of forming a gate array type integrated circuit, characterized in that a connection of a resistance element corresponding to a magnitude of a current value of the ECL circuit and the emitter follower output circuit is selected.