JPS6016022A - Complementary logic circuit - Google Patents

Abstract

PURPOSE:To attain low power consumption and high speed operation by constituting a logic circuit with a 1st stage circuit comprising N and P type MIS transistors (TR) and an output circuit comprising a pnp and an npn bipolar TRs so as to form the output circuit as a common emitter circuit. CONSTITUTION:The 1st stage circuit of the logic circuit is constituted by the N and P type MIS TRs Q3, Q4 of lateral structure. Further, the output circuit is constituted by the pnp and npn TRs Q5, Q6 of vertical structure and the 1st stage circuit and the output circuit constitute a complementary inverter circuit. Bases of the TRs Q3, Q4 of the circuit are connected in common and an input signal IN is applied to the cnnecting point. A base of the TRs Q5, Q6 is connected to each drain of the TRs Q3, Q4 and power supplies V+, V- are connected to each drain of the TRs Q3, Q4 and each emitter of the TRs Q5, Q6. Then the source of the TRs Q3, Q4 and the collector of the TRs Q5, Q6 are connected in common, and an output signal OUT is outputted thereby attaining low power consumption of the circuit and high speed operation.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to complementary logic circuits, and in particular to complementary logic circuits that enable high-speed operation with low power consumption by combining MIS transistors and bipolar transistors or static induction transistors. Concerning type logic circuits.

[Technology background]

In general, C-MIS type logic circuits have extremely low power consumption, but have low load driving ability and relatively slow operation. On the other hand, bipolar logic circuits using bipolar transistors and the like have a drawback that they have a high driving ability for loads and can be expected to operate at high speed, but they also consume large amounts of power. Therefore, if a logic circuit that combines the advantages of both logic N-paths can be constructed, it will be possible to significantly improve the performance of computers and other digital systems.

[Conventional technology and problems]

Figure 1 shows a C-M as an example of a conventional logic circuit.
An IS non-inverting circuit is shown. The circuit in the figure consists of two C-M
It is constructed by cascading IS type inverter circuits.

Each C,,-MI S-type inverter is connected to p-channel MIS) range meta 9x and n-channel MIS, respectively.
S) transistor Q2, and p-channel MIS) transistor Q1/and n-channel MIS) transistor Q2. The input signal IN is applied to each transistor Q1 and Q2 of the first stage inverter, and the inverted output of the first stage inverter is applied to each transistor Q! of the next stage inverter. and entered into the dart of Q2,
The output signal OUT is transmitted through transistors Qt and Q! ' are taken out from the interconnected drains of '.

In the circuit shown in FIG. 1, when the input signal IN is at a high level, the transistor Q2 of the first stage inverter is turned on, the transistor Qx' of the next stage inverter is turned on, and the output signal OUT becomes high level. Conversely, when the input signal IN is at a low level, the transistor Qt of the first stage inverter is turned on, the transistor (h) of the next stage inverter is turned on, and the output signal OUT becomes a low level.
The circuit shown operates as a non-inverting circuit. And the first
In the circuit shown in the figure, when the input signal IN is at a high level, the transistor Q of the first stage inverter! and transistor Q of the next stage inverter! is cut on, and when the input signal IN is at a low level, transistor Q2 of the first stage inverter and transistor Ql of the next stage inverter are cut on. Therefore, in a steady state where the input signal is maintained at a high level or a low level, almost no power It consumes power only in transient conditions. Therefore, by using the circuit shown in FIG. 1, it was possible to construct a low power non-inverting logic circuit km.

However, in the conventional type, since the transistors Ql+Qz and Q11Q2 of each inverter are both lateral MIS transistors, the current flows through the surface of the semiconductor substrate, and the on-resistance becomes very high, causing the load capacitance C
There was an inconvenience that the operating speed decreased due to L.

In addition, it has been considered to increase the channel width in order to reduce the on-resistance in lateral MID transistors, but increasing the channel width increases the input capacitance, that is, the dart capacitance, which would not increase the operating speed. I couldn't. Further, in the conventional circuit, in order to increase the driving capability, the threshold value of each transistor is made small so that the on-side transistors are sufficiently saturated in a steady state. Therefore, in the transition state,
There is a problem in that the power consumption of the circuit increases due to the large wasteful transient current flowing from the power supply 1-1 to V- during the on-on state.

[Purpose of the invention]

In view of the problems in the conventional type described above, an object of the present invention is to provide a complementary logic circuit with an initial stage circuit having n-type and p-type MIS transistors and a p-type MIS transistor.
Extremely low power consumption is achieved based on the concept of constructing a complementary circuit using an output circuit having np type and npn type bipolar transistors or static induction transistors, and making the output circuit a common emitter (source) type circuit. The object of the present invention is to provide a logic circuit that is simple yet capable of high-speed operation.

[Structure of the invention]

According to the present invention, the first stage circuit has an n-type MIS transistor and a p-type MID transistor, and a pnp-type bipolar transistor (or a p-type static induction transistor and an npn-type bipolar transistor). transistor (or n-type static induction transistor), the darts of each MIS) transistor are connected to each other to receive an input signal, and the n-type and p-type
The drains of the MIS transistors of the pnp type and npn type bipolar transistors (
The collector (drain) of each bipolar transistor (transistor) and the source of each MIS transistor are connected to each other to form an output. This is achieved by providing a complementary logic circuit characterized in that power is supplied to the emitter (source) of each bipolar transistor (static induction transistor).

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 2 shows a non-inverting circuit as the most basic complementary logic circuit according to an embodiment of the present invention. The circuit in the figure is an n-type MI with a lateral structure.
S) Transistor Q3, p-type MI containing lateral structure
D) Transistor Q4, for example vertical structure fr:,i
A pnp transistor Qs having a vertical structure and an npn transistor Q6 having, for example, a vertical structure are provided. Transistors Q5 and Qs are, for example, a pnp bipolar transistor and an npn bipolar transistor, respectively. The dart of MIS transistor Q3 and the gate L of MIS transistor Q4 are connected to each other and input signal IN is applied. , MIS) The drain of transistor Q3 is connected to the pace of transistor Q5, and MIS
The drain of S transistor Q4 is connected to the pace of transistor Q6. MIS) The sources of transistors Q3 and Q4 and the collectors of transistors Q11 and Qs are commonly connected and output signal 01JT is taken out. Also, the emitters of transistors Qs and Qs are respectively connected to the high potential feed of the power supply and the low potential side V- of the power supply.

In the circuit of FIG. 2, when the input signal IN is at a high level, the n-type MTS transistor Q3. turns on and pn
The pace of p-type transistor Q8 is reduced to a low level.

As a result, the transistor Qs is also turned on and the output signal OUT becomes high level. At this time, both the p-type MIS transistor Q4 and the npn-type transistor Q6 are in a cutoff state.

Conversely, when the input signal IN is at a low level, the p-channel M
IS) Since the lansostar Q4 is turned on and pulls up the pace voltage of the j5 npn type transistor Q6, the transistor Q6 is also turned on, and the output signal OUT becomes a low level.

In this case, the n-channel MIS transistor Q3 and the pnp transistor Q5 are both cut off.

As is clear from the above description, the circuit of FIG. 2 operates as a non-inverting circuit, but when the input signal IN is at a high level, both transistors Q4 and Qs are cut off,
Since both transistors Q3 and Qs are cut off when the input signal IN is at a low level, little power is consumed in the steady state. Also, the transistor Qs
Since both Qs and Qs are bipolar transistors, the on-resistance can be made very low, and high-speed operation can be performed without being affected by load capacitance. In addition, transistors Qs, Qs/Qa, and Q4 are not turned on in synchronization, and the low resistance when transistors Q3/Q4 are on causes a shunt between the collector pastes of transistors Qs/Qa. Especially transistor Q
The oversaturation phenomenon in the on state, which would be a problem when s/Q a is a bipolar transistor, is significantly alleviated, further promoting high-speed operation.

Note that in the circuit shown in Figure 2, the output stage transistor Q
By inserting a resistor R between the pace and emitter of , and Qs, the turn-off time of each of these transistors can be made faster, and the operating speed of the logic circuit can be greatly increased.

In addition, in the circuit shown in Fig. 2, the load on each MIS transistor Q3 and Q4 becomes only transistors Q5 and Qs, which becomes extremely light.
There is no need to increase the driving capacity of the transistor. Therefore, there is no need to lower the threshold voltage of each lateral MIS transistor to ensure a large on-on state, and it is possible to reduce the wasted current flowing from the power supply V+ to V- during a transient.9 Circuit consumption Electric power can be extremely reduced. In addition, generally MIS-FET
In this case, there is a phenomenon in which the dirt threshold voltage increases greatly as the potential difference between the source and the substrate increases, that is, the substrate effect.

In the circuit of FIG. 2, the substrate of the n-channel MIS transistor Q3 is connected to the low potential side of the power supply, and the source of the transistor Q3 is connected between the source and drain of the p-channel MIS transistor Q4 and between the source and drain of the npn) transistor Q6. The low potential side of the power supply V-
, the voltage between the source and the substrate is larger than in the conventional C-MI8 circuit. Similarly, the voltage between the source and the substrate of p-channel MIS transistor Q4 is increased. Therefore, when a conventional C-MIS circuit and a circuit according to the present invention coexist on the same chip, a This is rarely a problem due to the buffer effect of the transistor. In addition, even in the conventional C-MI8 circuit, a Vth shift occurs due to the stacking of transistors in a large-power NAND gate, resulting in differences in operating speed depending on the input terminal, but in the circuit according to the present invention, a multi-input dart is configured. However, it has the advantage that there is almost no problem due to the same effect.

As the transistors QII and Q6 in the circuit of FIG. 2, various transistors such as those shown in FIG. 3 can be used. Figures 3(&) and (b) use bipolar transistors as each transistor.
c) and (d) each transistor is 5IT (St
aticInduction Tranal@tor
: Indicates a device using a static induction type transistor). Note that the SIT needs to be designed as a normally-off type element.

If a normally-on type SIT is adopted,
The drain of each MI8) transistor in the previous stage in FIG. 2 may be connected via a resistor R to the high potential side of a higher power supply or to the low potential side of a lower power supply.

FIG. 4 shows an OR dart circuit as another embodiment of the present invention. The circuit in the figure consists of two n
Channel MID) transistors Q7 and Qll, p-channel MIS) transistor Q9 connected in series with each other
and Qlo %, and includes a pnp type transistor Qll having, for example, a vertical structure and an npn type transistor Q12 having, for example, a vertical structure. The sources of transistors Q7 and Q8 are connected to the collectors (drains) of transistors Qst and Q12 and the source of transistor Q9. One input signal IN1 is applied to the dart of transistor Q7 and the dart of transistor Q1o, and the other input signal IN1 is applied to the dart of transistor Q8 and the dart of transistor Q9. Transistors Q1t and Q! The emitters (sources) of g are respectively connected to the high potential (1!IV+) of the power supply and to the low potential side V- of the power supply.

In the circuit of FIG. 4, input signals INl and IN,
When both are at low level, p-channel MIS transistors Q9 and Qso are turned on, and therefore transistor Q12 is turned on, so that output signal OUT becomes low level. On the other hand, if at least one of the input signals IN1i or IN is at a high level, the
When either transistor Q11 or transistor Q8 is on, the pace voltage of transistor Q11 is lowered. At the same time, Q91Q
1G is turned off. Therefore, the transistor Q
! t turns on (hz turns off and the output signal OUT
is at a high level. Therefore, the circuit of FIG. 4 operates as an OR dart.

FIG. 5 shows an AND dart circuit as yet another embodiment of the present invention. The circuit in the figure consists of n-channel MIS) transistors qts and Q14, which are connected in series with each other.
p-channel MI8) 57 Zosta Q15 and Q16 connected in parallel with each other, and pnp and npn
type transistor Q1? and Qts. The detailed structure and operation of this circuit can be easily inferred from what has been described above regarding the circuit of FIG. 4, so theory F! Omit A.

〔Effect of the invention〕

As described above, according to the present invention, complementary logic can be implemented using an initial stage circuit including an n-type MIS transistor and a p-type MIS transistor, and an output circuit including a pnp bipolar transistor and an npn bipolar transistor. By configuring the circuit, it is possible to configure an extremely low power logic circuit that consumes almost no current in a steady state. Further, by using a vertical transistor in the output stage, an extremely high-speed logic circuit can be realized without reducing the operating speed due to the influence of load order. The local speed of the MIS is such that the load on the front-stage MIS transistor with a lateral structure is only the pace (dirt) of the rear-stage vertical transistor.
S) This becomes more noticeable as the load on the transistor becomes lighter.

In summary, according to the present invention, a logic circuit is provided which has low power consumption equivalent to that of a C-MIS circuit, high speed, and drive capability.

[Brief explanation of the drawing]

Figure 1 shows a C-MI as an example of a conventional logic circuit.
An electric circuit diagram showing an S-type non-inverting circuit, FIG. 2 is a first embodiment of the present invention.
FIG. 3 is an electric circuit diagram showing the logic N path according to the embodiment, FIG. 3 is an electric circuit diagram showing the types of transistors used in the circuit of FIG. 2, and FIGS. FIG. 2 is an electrical circuit diagram showing an embodiment. Qt + Qt + Q4 v Qe y Qto e
Q15 r Q+a°3p channel MIS) transistor, Q2 p Qg pQs+Qy + Qs v
Qls + Qt4-n channel MIS) transistor, Qs, Q111Q17... pnp type transistor,
Qe + Qu + Qts-npn type transistor. Patent applicant Fujitsu Limited Patent agent Akira Aoki Patent attorney Kazuyuki Nishidate 1) Yukio Patent attorney Akira Yamaguchi Figure 1 Figure 2 Figure 3 (a) (c) ( b) (d) 1N: 1”

Claims (1)

[Claims] L An initial stage circuit having an n-type MTS) transistor and a p-type MIS) transistor, a pnp-type bipolar transistor (or p-type static induction transistor), and an npn-type bipolar transistor (or n 1. an output circuit having a type of static induction transistor); The darts of each MIS) transistor are connected to each other to receive input signals, and the drains of the n-type and p-type MIS) transistors are connected to the corresponding core pnp-type and np-type
It is connected to the pace (dart) of the n-type bipolar transistor (p-type and n-type static induction transistor), and the collector (drain) of each bipolar transistor (static induction transistor) and the source of each MIS transistor are mutually connected. A complementary logic circuit characterized in that the bipolar transistor (the emitter of the electrostatic induction transistor) is connected as an output and supplies power to the emitter (source) of each bipolar transistor (electrostatic induction transistor). A complementary logic circuit according to claim 1, characterized in that: