JPS6016021A - Complementary logic circuit - Google Patents

Abstract

PURPOSE:To attain high speed operation with low power consumption by constituting a logic circuit with the 1st stage circuit comprising MIS transistors (TRs) and an output circuit comprising a complementary circuit so as to form its output circuit as a common emitter (source) type. CONSTITUTION:Bases of p-channel and n-channel MIS TRs Q3, Q4 of lateral structure are connected mutually and an input signal IN is inputted to the base. The TRs Q3, Q4 form the first stage circuit of the MIS inverter circuit as the logic circuit. Base of pnp TRQ5 and npn TRQ6 of vertical structure are connected respectively to sources of the TRs Q3, Q4 and each source is connected respctively to a power supply V+ and V-. Moreover, drains of the TRs Q5, Q6 and an output signal OUT is outputted from the connecting point. Further, the TRs Q5, Q6 are formed as the output circuit so as to attain the low power consumption of the circuit thereby attaining high speed operation.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a complementary logic circuit, and in particular to a complementary logic circuit that can operate at high speed while maintaining low power consumption by combining an MIS transistor and a bipolar transistor or a static induction transistor. This paper relates to complementary logic circuits that have been made possible.

[Technology background]

Generally, C-MIS type logic circuits have extremely low power consumption, but have low load driving ability and relatively low operating speed. On the other hand, bipolar logic circuits using bipolar transistors have a high drive ability for loads and can be expected to operate at high speed, but they have the drawback of high power consumption. If a logic circuit can be constructed that has both of these features, it will be possible to significantly improve the performance of converters and other digital systems.

[Conventional technology and problems]

Figure 1 shows a C-M as an example of a conventional logic circuit.
An IS type inverter circuit is shown. The circuit in the figure is composed of a p-channel MIS transistor Q and a (Jn-channel MIS) transistor Q2.Input signal I
N is each transistor Q.

and Q2, and the output signal OUT is taken out from the drain of each commonly connected transistor. The source of the transistor Q is connected to the tiO high potential side (2), and the source of the transistor Q2 is connected to the low potential side (3) of the power supply.

In the circuit shown in FIG. 1, when the input signal IN is at a high level, the unchannel MIS transistor Q2 is turned on and the output signal OUT is at a low level. Conversely, when the input signal IN is at a low level, the p-channel M/S transistor Q1 is turned on and the output signal OUT is at a high level. (3) In the circuit of FIG. 1, when the input signal IN is at a high level, the p-channel MIS transistor Q.

When the input signal IN is at a low level, the unchannel MIS) and register Q are cut off, so in a steady state when the input signal IN is maintained at a high or low level, almost no power is consumed. However, in the conventional type, it is possible to construct an extremely low power logic circuit by using the circuit shown in FIG. , Q2 are both lateral MIS (MIS) transistors, so current flows through the surface of the semiconductor substrate, resulting in a significantly high on-resistance, which causes the disadvantage that the operating speed decreases due to the load capacitance CLK. Maπ, lateral MIS
) In order to reduce the on-resistance in a transistor, it was considered to increase the channel width, but increasing the channel width increases the input capacitance, that is, the gate capacitance, and it is not possible to increase the operating speed that much (4) Shigeru: In the conventional circuit described above, in order to increase the driving capability, the threshold voltage of each transistor is made small so that the on-side transistors are sufficiently saturated in a steady state. Therefore, in the transition state, there is an inconvenience that the power consumption of the circuit increases due to the large wasteful transient current flowing from the power supply V0 to the power supply V- during the on-on state.

[Purpose of the invention]

An object of the present invention is to solve the problems of the conventional type described above, and to provide a complementary logic circuit with a first stage circuit having p-type and n-type MIS transistors and a pnp
A complementary circuit is constructed using an output circuit having a type ↓ type and an npn NIL bipolar transistor or a static induction transistor, and the output circuit is connected to an emitter (
The object of the present invention is to provide a logic circuit that can operate at high speed while consuming extremely low power, based on the concept of a grounded source circuit.

[Structure of the invention]

According to the present invention, this purpose is achieved by providing an initial stage circuit having a p-type MIS) transistor and a pnp-type bipolar transistor (or p-type MIS) and a pnp-type bipolar transistor (or
n-type bipolar transistor (or n-type static induction transistor)
the gates of each MIS) transistor are connected to each other to receive an input signal, and the sources of the p-type and n-type MIS) transistors are connected to the corresponding pnp-type and npn-type It is connected to the base (gate) of the bipolar transistor (p-type and rlM static induction transistor), and the collector (drain) of each bipolar transistor (static induction transistor) and each MI
S) Connect the drains of the transistors together as an output,
An object of the present invention is to provide a complementary logic circuit characterized by supplying power to the emitter (source) of each bipolar transistor (silent conductive transistor).
is achieved.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 2 shows an inverter circuit as the most basic complementary logic circuit according to an embodiment of the present invention. The circuit in the figure is a p-type M having a lateral structure.
IS) Transistor Q3 n-type Δ/ with lateral structure
11IS) A transistor Q includes a pnp transistor Q5 having a vertical structure, for example, and an npn transistor Qge having a vertical structure, for example. Transistor Q5 and Qa rs each for example PNP
type bipolar transistor and npn type bipolar transistor. The gate of the transistor Q3 (λ=fIS) and the gate of the transistor Q4 (MIS) are connected to each other and an input signal IN is applied thereto. The source of MIS) transistor Q is connected to the base of transistor Q, and the source of MIS) transistor Q4 is connected to the base of transistor Q6. Drains of MIS transistors Q and Q4 and transistor Q5
The collectors of Q6 and Q6 are commonly connected (7) and the output signal OUT is taken out. Further, the emitters of transistors Q5 and Q6 are respectively connected to the high potential side V of the power supply and the low potential side - of the power supply.

In the circuit shown in Figure 2, when the input signal IN is at a high level, the n-type M/S transistor Q4 is turned on and npn
Pulls the base of transistor Q6 high. As a result, the transistor Q6 is also turned on and the output signal O
UT becomes low level.

At this time, both the p-type M-type S transistor Q and the p-type PNP transistor Q5 are in the cut-off state. Conversely, when the input signal IN is at a low level, the p-type MIS transistor Q3 is turned on, lowering the base voltage of the pnp-type transistor Q, so that the transistor Q5 is also turned on, and the output signal OUT is at a high level. In this case V
In-type MIS) transistor Q4 and npn-type transistor Q6 are both cut off.

As is clear from the above explanation, the circuit of FIG. 2 operates as an inverter, but when the input signal IN is high (8) level c/'), the transistors Q3 and Q5
When the input signal IN is at a low level, both the transistors Q4 and Q6 are cut off. Therefore, in the steady state, almost no power is consumed. In addition, transistors Q and Qata are both bipolar transistors, and can also be made into vertical transistors, making it possible to significantly lower the on-resistance, allowing high-speed operation without being affected by the load capacitor. be able to. -t7c, transistors Q3/Q, 6 and Q4 are not turned on synchronously, and the low resistance when transistors Q3/Q4 are on causes a shunt between the collector bases of transistors Q5/Qa. In particular, the transistor Qs
The oversaturation phenomenon in the on state, which would be a problem when /Q6 is a bipolar transistor, is significantly alleviated, further promoting high-speed operation.

In addition, in the circuit shown in Fig. 2, the output stage transistor Q
5 By inserting a resistor R between the base and emitter of Q6, it is possible to make the turn-off time of each of these transistors faster, and the operating speed of the logic circuit can be increased. .

In addition, in the second circuit, the load on each MIS transistor Q and Q4 is reduced to only transistors Q5 and Q6, which makes it extremely light, so it is necessary to increase the driving capacity of each MIS transistor. There is no. Therefore, there is no need to lower the threshold voltage of each MIS transistor to ensure a large on-on state, and it is possible to reduce the wasted current flowing from the power supply V+ to V- during a transient, which greatly reduces the power consumption of the circuit. In general, MI S-FE can be reduced.
In T, there is a phenomenon in which the gate threshold voltage increases greatly as the potential difference between the source and the substrate increases, that is, the substrate effect.

In the circuit shown in FIG. 2, the substrate of the n-channel MIS transistor Q is connected to the low potential side V- of the power supply, and the source of the transistor Q4 is connected between the base and emitter during a transient. Power supply V-V
Because of the r-connection, the voltage between the source and the substrate is greater than in conventional C-MIS circuits. p
Similarly, the voltage between the source and the substrate of the transistor Q3 (channel MIS) is also increased. Therefore,
When a conventional C-MIS circuit and a circuit according to the present invention coexist on the same chip, the vt
Although h-shift occurs, in the circuit configuration according to the present invention, it hardly becomes a problem due to the buffer effect of the vertical transistor. In addition, even in conventional C-MIS circuits, a Vth shift occurs due to the stacking of transistors in a large-power NAND gate, resulting in a difference in operating speed depending on the input terminal, but in the circuit according to the present invention, a multi-input gate, etc. It has the advantage that there is almost no problem in achieving the same effect even if the configuration is configured as follows.

Each transistor Q5 in the circuit of FIG. Q.

For example, various types can be used, such as the one shown in FIG. In Figures 3(a) and 3(b), bipolar transistors are used as each transistor, and (1)
1) Figure 3 (c) s (d) shows BI as each transistor.
T(5tatic Induction Tran+5
1stor: A 7C type transistor using a static induction type transistor is shown. Note that it is necessary to design it as a 5ITtl normally-off type element.

When adopting a normally-on type SIT!
! The source of each MIS transistor in the previous stage in FIG. 2 may be connected via a resistor R to the high potential side of a next higher power supply or to the lower potential side of a next lower power supply.

FIG. 4 shows a NAND gate circuit as another embodiment of the invention. The circuit in the figure consists of two p-channel MIS transistors Q7 and Q8 connected in parallel to each other.
n-channel MIS) transistors Q connected in series with each other
, L and Q, o, and, for example, a pnp type transistor Q11 and, for example, an npn type transistor Ql1
1. Tiger.

The drains of transistors Q7 and Q8 are connected to transistor Q.
o↓ and Q10 collector (drain) and tran-
)X is connected to the drain of Q9. 1 (12) input signals IN, are applied to the gate of transistor Q, and to the gate of transistor Q+o, and the other input signal I
N2 is applied to the gate of transistor Q8 and the gate of transistor Q. The emitters (sources) of transistors Q1□ and Q+z are connected to the high potential side V+ and the low potential side V- of the power supply, respectively.

In the circuit of Fig. 4, the input signal IN, the input signal IN,
If both are at high level, then n-channel MIS) transistor Q, Omachi Q, and so on. is turned on, and therefore the transistor Q1□ is turned on, so the output signal OUT becomes low level. On the other hand, if at least one of the input signals IN1 or IN is at a low level, the transistor Q
7 Either ↓ or Q8 turns on and transistor Q
Lower the base voltage of 1□. At the same time, Qs +
Qlo is turned off. Therefore, the transistor Q1□ is turned on! DQ,2 is turned off and the output signal OUT becomes high level. Therefore, the circuit of FIG. 4 operates as a NAND gate.

(13) Figure m5 shows a NOR gate circuit as yet another embodiment of the present invention. The circuits in the figure are connected in series with each other.
CP channel MIS) transistors Q+s and Q,4,
It includes n-channel MIS transistors Qss and Q16 connected in parallel with each other, and pnp type transistors and npn type transistors Q+y and Q+s. The detailed structure and operation of this circuit can be easily inferred from what has been described above with respect to the circuit of FIG. 4, so a detailed explanation thereof will be omitted.

〔Effect of the invention〕

In this way, if the present invention is applied, for example, p-type lateral M
Since a complementary logic circuit is constructed using an initial stage circuit consisting of an IS) transistor and an n-type lateral MIS transistor, and an output circuit consisting of a pnp bipolar transistor and an npn type σ) bipolar transistor, in a steady state, An extremely low power logic circuit can be constructed without consuming much current. However, by using a vertical transistor after the output, there is no reduction in operating speed due to the influence of rainbow load capacitance, and extremely high
A (1,4) association logic circuit can be realized. This high-speed performance becomes even more remarkable because the load on the lateral MIS transistor in the previous stage becomes lighter than the load on the lateral MIS transistor, which is only the base (gate) of the vertical transistor in the latter stage.

In summary, according to the present invention, a logic circuit is provided that has low power consumption equivalent to that of a C-MIS circuit, yet has high speed and high drive ability.

[Brief explanation of the drawing]

Figure 1 shows a C-MI as an example of a conventional logic circuit.
An electric circuit diagram showing an S-type inverter circuit, FIG. 2 is an electric circuit diagram showing a logic circuit according to an embodiment of the present invention, and FIG. 3 is an electric circuit diagram showing the types of transistors used in the circuit of FIG. 2. Figures 4 and 5 are electrical circuit diagrams showing other embodiments of the present invention. Qlw Q2+ Qy+ Qs+ Q131 Q10
: P channel MIS) transistor, Q! , Q4 lQ91 QIOI Q151 Qls
: n channel MIS) transistor, (15) Qs + Qot Q17 : p n pW ) 5
xi, Q6+ Qsx+ QCs: n p
n-type transistor. Patent applicant Fujitsu Ltd. Patent attorney Akira Yoiki Patent attorney Kazuyuki Nishidate 1) Yukio Patent attorney Akiyuki Yamaguchi (16) Figure 2 Figure 3 (a) (c) ( b) (d) ■ ■ Figure 5 Helmet Dζ1

Claims (1)

[Claims] 1. A first stage circuit including a p-type MIS transistor and an n-type MIS transistor, and a pnp W bipolar transistor (or a p-type static induction transistor)
and an npH-type bipolar transistor (or an n-type static induction transistor),
The gates of each MIS) transistor are connected to each other to receive an input signal, and the sources of the nine n-type MID) transistors are connected to the corresponding pnp and npn bipolar transistors (pm and nw static), respectively. The collector (drain) of each bipolar transistor (electrostatic induction transistor) and the drain of each MIS transistor are connected to each other to form an output. A complementary logic circuit characterized by supplying power to the emitter (source) of an electric induction transistor. 2. The complementary logic circuit according to claim 1, wherein the bipolar transistor or the electrostatic induction transistor is a vertical transistor.