JPS595748A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To realize a relatively high operation speed and to reduce an input current, by using a CML gate. CONSTITUTION:An input level conversion part 1 receives and converts an input signal at a TTL level to a signal level conforming to the logical signal of an internal logical gate part 2. The internal logical gate part 2 is composed of the CML logical gate for high-speed processing to perform desired logical processing operation. An output level conversion part 3 receives and converts a signal which is generated by the internal logical gate part 2 and to be outputted and the signal is converted to the TTL signal level, to output to external terminals OUT1-OUTn. Thus, the CML gate is used to increase the operation speed as compared with a TTL gate, and a diode logical circuit similar to the TTL gate of an LS type is usable for the input level converting circuit, so the input current is reduced to increase the number of fan outs correspondingly.

Description

[Detailed description of the invention] The present invention relates to a semiconductor integrated circuit device.

The logic LSI (large scale integrated circuit) is used as an internal logic gate, and the internal logic gate is OML (Ourrent Mode Logi).
c) or BOL (Emitter 0ulple
d Logic), and the input/output section is T
L (Transistor
The IEBEJournal ofSolid-8 is equipped with a signal level conversion circuit compatible with the IBEJournal ofSolid-8, which is equipped with a signal level conversion circuit compatible with the TTL gate LSI.
Volsc-14m5 from tate 0ircuits magazine
(1979 lθ month issue) pps18-822 smell 1
It is publicly known.

The input level conversion circuit used in this LSI is a transistor Q, as shown in FIG. and resistance van,. ,
It is composed of R.

Through research conducted by the inventor of the present application, it has become clear that this input level conversion circuit has the following drawbacks.

The input voltage-current characteristic of the level conversion circuit is as shown by the solid line in FIG.

As is clear from this characteristic, the input current IIL increases when the TTL signal is set to low level.

Therefore, if, for example, an LS (Low Power Schottky) type TTL circuit is used as the TTL circuit for forming the TTL signal, the number of fan-outs will be three at most. Also, because the input current IL is large, the power consumption at the input section becomes large.

In general, the logic threshold voltage becomes 1 volt or less, and the low level side margin becomes small.

Furthermore, when the input signal changes, the input current IIL flows or does not flow, causing a voltage fluctuation due to a relatively large switching current in the power supply voltage line of the internal logic block. If the signal amplitude margin is reduced, it may also become a cause of malfunction.

An object of the present invention is to provide a semiconductor integrated circuit device that is relatively high-speed and requires a small input current.

Other objects of the invention will become apparent from the following description and drawings.

Hereinafter, this invention will be explained in detail together with examples.

FIG. 3 shows a block diagram of an embodiment of the present invention.
ing.

In the figure, each circuit block surrounded by a dotted line 1 is formed on a single semiconductor substrate by a known semiconductor integrated circuit manufacturing method.

The semiconductor integrated circuit device LSI of this embodiment includes an input level conversion section 1, an internal logic gate section 2, and an output level conversion section 3.
It is composed of.

The input level converting section] receives an input signal of TTL level and converts it to a signal level according to the logic signal of the internal logic gate section 2. The internal logic gate section 2 is composed of CML (or EOL) logic gates for high-speed logic processing, and performs desired logic processing operations. Further, the output level converter 3 receives the signal to be output formed by the internal logic gate 2 and converts it to T.
'r It is converted to an L signal level and output from the external terminal OUT or OUT.

In this embodiment, as a logic gate that performs logic processing,
By using OML (or EOL') gate,
This is intended to achieve higher speed than when using a T '1'' L gate.
Since a level conversion circuit is also provided for the circuit, when viewed from the outside, it can be treated in the same way as a widely used TTL gate semiconductor integrated circuit.

FIG. f84 shows a circuit diagram of an embodiment of the input level conversion circuit.

An input signal at the 'rTL level is applied to the external terminal IN. This input signal is input to a diode logic circuit composed of a resistor R8 and a diode D, which operates at the same power supply voltage vl (5 volts) as the TTL circuit. A diode D for clamping the undershoot of the input signal is connected between the terminal IN and the ground potential.
There are 1.

Such a diode logic block is similar to the input logic block in a known LS type TTL circuit. The output signal of the diode logic circuit is transmitted to a transistor Q for level conversion.

is applied to the base of The emitter of this transistor Q is connected to the cathodes of diodes D and I, and both are in a differential configuration.

A resistor L is provided between the connection point between the emitter of the transistor JQ+ and the cathode of the diode D and the ground potential of the circuit. Also, the collector of transistor Q1 is connected to the power supply voltage (eg, 2 volts) terminal V of the internal OML (or ECL) gate.

connected to. A load resistor R1 is provided between the anode of the diode D and the power supply voltage terminal vf,
Forming a level-converted output signal.

The internal OML gate may include, but is not limited to, a differential type transistor Q that constitutes a logic block.

or Q4 and these transistors Q, etc.
A resistor R6 is provided between the common emitter of the transistors Q4 and the ground potential of the circuit, and a collector load resistor kL4 of the transistor Q4 is provided. R11. The collectors of the transistors Q, Q, are shared and connected to one load resistor R4, and the collector of the transistor Q4 is connected to the other load resistor R3. And again, transistor Q! .

A reference voltage Vref as a logic threshold is applied to the base of the transistor Q and the base of the transistor Q, respectively.

The number of the input transistors Q, , Qt, etc. is provided in accordance with the fan-in number of the gate.

The internal logic gate 2 is formed by forming a large number of the above-mentioned OML gates, but is not particularly limited, and the connection between each gate is formed by a master slice method so as to have the desired logic processing function. be. As a result, it is possible to improve the mass productivity of a wide variety of semiconductor integrated circuit devices.

FIG. 5 shows a circuit diagram of an embodiment of the output level conversion circuit.

The signal formed by the OML gate to be output is input to the differential transistor circuit operating at the internal power supply voltage V2. This differential transistor circuit is similar to the Shiki OML gate.

In that the diode D4 for level shifting the output high level (Vt level) is provided at the collector of the transistor Q that forms the output signal.
This is different from the above OML gate.

The collector output of the above transistor Qs is transistor'
Q? It is transmitted to the next output circuit through an emitter 7 lower circuit consisting of a resistor kL1 (1).

The output circuit is composed of a fuse split transistor Qll in a known TTL gate and a totem pole type output circuit, and together with the emitter follower circuit, these are connected to the same power supply voltage vI (
5 volts).

Note that the transistor Q provided between the base and emitter of the output transistor Q4n, and the resistor R1□R,s are provided to form a constant current circuit and to speed up the switching of the transistor Q+n to off. There is. Also, transistor QI! The resistance ratio 4 provided between the base and emitter of is a bias resistor, and this transistor Q+
A diode D is provided between the base of transistor Q8 and the collector of transistor Q8. Provided for faster switching off.

Therefore, in the semiconductor integrated circuit device of this embodiment, after receiving TTL level signals, the OML gate also performs logic processing on these signals internally, and then the output signals are converted to TTL.
Since the output is returned to the same level, it can be handled in an appearance equivalent to a TTL gate semiconductor integrated circuit device, and can operate at a higher speed than a TTL gate semiconductor integrated circuit device.

Moreover, the input level conversion circuit is an LS type TT.
Since a diode logic circuit similar to the L gate is used, the input characteristics can be made equal to those of a general L8-TTL gate, as shown by the dotted line in FIG. As is clear from this characteristic, the input current "IL" is a small current value of 0.5 mA or less. This means that the semiconductor integrated circuit device can have a large fan-out number.This input current "IL" is supplied from a different input from the internal logic gate, the power supply voltage V for the output level conversion circuit. Voltage fluctuations due to switching current will not adversely affect internal logic gates.

Furthermore, the logic threshold voltage in the input level conversion circuit is approximately 1.5, as is clear from the characteristic diagram in Figure 2.
volts and can be matched with logic threshold voltages of TTL circuits. Therefore, the level margin on the low level side with respect to the logic threshold voltage -j can be increased, so that the noise resistance at the input section can be improved.

For example, if the high level of the internal logic signal is set to 2.0 volts and the level of the internal logic signal is set to 1.4 volts, the level converter will set the resistor R1 to 1.3 Ω and the resistor R3 to 1.6 volts.
It can be easily formed by making it like Ω. In this level converter, the transistor Q and the diode D3 operate in a differential manner, so when viewed from the internal power supply voltage terminal v2, only a small switching current flows, reducing the fluctuation width of the power supply voltage V. It is possible.

In this level converter, the output high level is determined by the internal power supply voltage V, and the output low level is determined arbitrarily by the ratio of the resistors) (..., R2 and the forward voltage of the diode D). It is configurable.

Furthermore, since the input level conversion circuit of this embodiment uses a differential circuit in the level conversion section, the signal transmission speed is increased.

This invention is not limited to the above embodiments.

For example, as shown in the embodiment circuit of FIG. 6, the input level converting circuit has an input section that includes a filter, a diode D1. D
, ' may also be used to add logical processing functions.

Furthermore, the level converter may replace the diode D with a transistor Q+'.

In this case, it is necessary to apply a predetermined reference voltage vref to the base of transistor QI'.

Further, a transistor Q is provided to prevent a switching current from flowing into the supply line of the power supply voltage v1 due to the switching operation in the level converter.

A dummy resistor R,' may be provided at the collector of the converter, or a current may be caused to flow through the converter regardless of the input level. Alternatively, the resistor R8 may be replaced with a constant current source.

Further, the internal logic gate can be modified as much as possible, such as by adding an emitter follower output transistor or by replacing the resistor R6 with a constant current source.

Furthermore, the output level conversion circuit may be of any type as long as it forms a TTL level output signal.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of the prior art, FIG. 2 is a characteristic diagram of an input level conversion circuit, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG. A circuit diagram showing one embodiment of an input level conversion circuit and an OML gate, FIG. 5 is a circuit diagram showing one embodiment of the output level conversion circuit, and FIG. 6 is another embodiment of the input level conversion circuit. FIG. 1... Input level conversion section, 2... Internal logic gate section, 3... Output level conversion section. Figure 3

Claims (1)

[Claims] 1. A diode logic block that receives TTI level signals and operates with a power supply voltage for the TTL circuit; Operates with the power supply voltage for the CML (or EOL) circuit, and the above internal OML (or EOL)
1. A semiconductor integrated circuit device comprising a level converting circuit configured with a differential circuit that forms an input signal level to the circuit. 2. The differential-1 path is a transistor whose base is stamped with the output signal of the diode logic block;
This transistor has a diode installed in a differential configuration, and a resistor that is commonly installed between the emitter of the transistor and the cathode of the diode. and the anode of the above diode and the internal OML (or BO
L) It consists of a resistor installed between the circuit power supply voltage and the input signal to the i0ML (or EOL) circuit described above is obtained from the connection point between the resistor cap and the anode of the diode. The first claim characterized in that
The semiconductor integrated circuit device described in Section 1.