JPS62166459A - Processor - Google Patents

Abstract

PURPOSE:To realize a high-speed processor by providing a data bus with a function for reading or writing data out of or in a memory. CONSTITUTION:The processor 1 is connected to the 1st memory 3 through the 1st bus 2 and connected to the 2nd memory 5 through the 2nd bus 4. The processor 1 fetches an instruction from the memory 3, but fetches no instruction from the memory 5. The processor, however, performs reading from and writing to the memory 5 except the instruction fetching as well as the memory 3. Consequently, while an instruction is fetched, the memory is read or written by the instruction, so the high-speed processor is realized.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to the structure of a processor, and particularly to a processor that enables high-speed processing.

(Prior Art) The processor currently in practical use is the so-called E-phono-Neumann computer J proposed by Phono Neumann, and when the processor fetches an instruction from memory, it also reads or writes data from memory. Sometimes they even run over the same bus.

(Problems to be Solved by the Invention) In the conventional example described above, when a processor reads or writes data from a memory, it interrupts instruction fetch and executes the read or write. However, the reason why the instruction fetch is interrupted is that the instruction fetch and data read or write are executed via the same bus.
There is no other reason to interrupt the fetch, and the processing of the processor will be slowed down by the amount of interruption.

(Means for solving the problem) The above problem can be solved by separating the bus for fetching instructions from the bus for reading or writing data from memory.

(Function) After separating the buses as described above, the instruction bus has the function of fetching instructions and the function of reading or writing data from memory, and the data bus has the function of reading or writing data from memory. By providing this function, a high-speed processor can be realized without losing the functions of conventional processors.

(Embodiment) FIG. 1 shows the connection between a processor and memory in which the present invention is implemented.

The processor 1 is connected to a first memory 3 via a first bus 2 and to a second memory 5 via a second path 4. Processor 1 fetches instructions from first memory 3 but not from second memory 5. but,
Regarding memory reading or writing other than instruction fetching, the second memory IJ5 can be executed in the same manner as the first memory 3.

Next, FIG. 2 shows the structure of this processor. The control calculation unit 10 analyzes instructions, executes calculations, transfers data, and controls the entire processor.

Register group 20 stores data necessary to control the processor. The first address bus buffer 30 and the second address bus buffer 40 are buffers for instructing addresses to external memory, and are connected to the outside of the processor via the first address bus 31 and the second address bus 41. 5 first data bus buffer 5
0 and the second data bus buffer 60 are buffers for inputting and outputting instructions and data between the external memory and the processor. Connected to the outside world. or,
The control calculation unit 10 controls a memory and the like external to the processor via an external control bus 11.

The register group 20 and each buffer 30 to 60 are connected to the control calculation section 10 by an internal control bus 81 and are controlled thereby. The first to fifth internal data buses 82 to 86 are
Control calculation unit 10, register group 20, and each buffer 30
Used for data transfer between .

Next, FIG. 4 shows some of the addressing modes of this processor in mnemonic format.

These are MOVE 1. M, r(n); stores the contents of the first memory 3 in a register (n) (n indicates a register number; the same applies hereinafter) in the processor 1 via the first bus 2;

MOVE 2 M, r(n); stores the contents of the second memory 5 in the register (n) in the processor 1 via the second bus 4;

However, the numbers 1 and 2 added to each mnemonic are used to distinguish whether the mnemonic regarding the addressing mode is an instruction for the first memory or an instruction for the second memory, and is applied to all addressing modes. Ru. In particular, PUSH.

As shown in Figure 2, it has two stack pointers (S, P, 1) and (S, P, 2) so that POP can be executed in both the first memory and the second memory. .
However, regarding Bart stack processing to save the return address of subroutine calls and interrupt processing, in order to distinguish whether it is stacked in the first memory or second memory, the external control bus is used as shown in Figure 2. 11 has a hard stack control line 90 for differentiation. From the above, if only instructions with the number 1 are added to the addressing mode instructions, and if the hard stack control line 90 is controlled so that the stack is stacked in the first memory, this processor is exactly the same as a normal processor. make a move.

Next, FIG. 3 shows how the processing power is improved. As shown in Figure 3.

After the instruction MOVE I M, r (n), to execute the instruction AND I M, r (n), fetch the instruction MOVF, 1 from the first memory 3 via the first bus 2, and The next instruction AND 1 cannot be fetched until after reading the contents of the first memory 3 via the first bus 2 according to the above instruction.

When executing the instruction AND 2 M, r(n) after the instruction MOVE 2 M, r (n), after fetching the instruction MOVE 2 from the first memory 3 via the first bus 2, Second
Since the process of reading the contents of the second memory 5 via the bus 4 and the process of fetching the next instruction, AND 2, from the first memory 3 via the first bus 2 can be executed simultaneously, the above process can be performed. Processing capacity improves by the amount of time that overlaps.

Next, the flow of instructions and data when executing the above instructions will be explained with reference to FIGS. 1 and 2. Registers (P, C,) in the register group 20 (where P, C, = Progr
am Counter) to the first address bus buffer 30 via the third internal data bus 84, and designating the transferred data as the address of the first memory 3 from the first address bus 31; The instruction MO stored at the specified address of the first memo I73
VE 2 is fetched to the control calculation unit 10 via the first data bus 51, first data bus buffer 50, and first internal data bus 82, and updates the registers (p, c,). Next, in accordance with the fetched instruction, the control calculation unit 10 transfers the data stored in the register (m) in the register group 20 to the second address bus buffer 40 via the fourth internal data bus 85. The transferred data is designated as the address of the second memory 5 from the second address bus 41, and the contents of the data M stored in the designated address of the second memory 5 are read. The data is stored in the register (n) in the register group 20 via the second data bus 61, the second data bus buffer 60, and the second internal data bus 83.

Furthermore, at the same time as this storage, the updated data in the registers (P, C,) is transferred to the first address bus buffer 30, similar to the MOVE 2 fetch described above.

The transferred data is transferred from the first address bus 31 to the first
Specify as the address of memory 3 and execute the next command AND
2 via the first data bus 51, first data bus buffer 50 and first internal data bus 82,
The data is fetched to the control calculation unit 10 and the registers (p, c,) are updated. Next, according to the two-part instruction, the data stored in the register (m) in the register group 20 is transferred to the second address bus buffer 40, and the transferred data is transferred from the second address bus 41 to the second memory. 5, and the contents of the data M in the second memory 5 are transferred to the second data bus 61, the second data bus buffer 760, and the second data bus buffer 760.
The contents of the register (n) in the register group 20 are transferred to the control calculation unit 10 via the internal data bus 83 and transferred to the control calculation unit 10 via the fifth internal data bus 86.
At the same time, the control calculation unit 10 executes AND processing of the data transferred via the second internal data bus 83 and the fifth internal data bus 86.
2, AND 2 as well as the updated register
The first instruction is fetched according to (p, c,), and instruction fetching and data reading or writing are repeated in the same manner.

According to this embodiment, the hard stack control line 90 allows
Since the hard stack destination can be selected from either of the two memories, an expandable system configuration is possible.

(Effects of the Invention) According to the present invention, it is possible to fetch an instruction and read or write the instruction to the memory at the same time, thereby realizing a high-speed processor.

2 is a diagram showing an outline of the connections.

FIG. 2 is a diagram showing an outline of the configuration of the present invention.

FIG. 3 is a diagram showing an outline of the movement of the bus according to the present invention.

FIG. 4 is a diagram showing a part of the addressing mode among the instructions related to the present invention.

DESCRIPTION OF SYMBOLS 1... Processor, 2... First bus, 4... Second bus, 20... Register group (especially (s, p, i
), (s, P, 2)) 90...Hard stack control line.

Claims (1)

[Claims] A bus for fetching instructions from memory and a bus for reading or writing data other than instructions from memory are separated, and the instruction bus has a function for fetching instructions and a function for reading or writing data from memory. 1. A processor characterized in that a data bus has a function of reading or writing data from a memory.