JPH04364533A - Stack controller - Google Patents

Abstract

PURPOSE:To speed up access by decreasing the frequency of access to stack data through a data bus. CONSTITUTION:This stack controller is equipped with a two-way buffer 22 which can perform first-in, last-out operation and first-in, first-out operation. Stack data are stored in this two-way buffer 22 and not stored in a data memory 14 as long as its capacity allows. The data bus 16 is dedicated to data access. When the stack data are generated exceeding the capacity of the two- way buffer 22, a stack pointer 21 operates and stack data expelled from the two-way buffer 22 are stored in the data memory 14. When the stack data stored in the two-way buffer 22 decreases, the stack data are read out of the data memory 14 again and put back to the two-way buffer 22.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stack control device that can efficiently execute a stack operation for the purpose of temporarily holding data when a microprocessor performs arithmetic processing.

0002

[Background Art] When a microprocessor performs arithmetic processing, it usually reads instructions stored in external memory, then reads data stored in external memory, performs predetermined arithmetic processing, and stores the data in external memory. perform an action such as When performing such an operation, an address signal for accessing the external memory is generated each time.

FIG. 2 shows a block diagram of a conventional device that performs such processing. The device shown is a microprocessor 1
-1 is connected to an external memory 2 via an address bus 3 and a data bus 4. The microprocessor 1-1 is provided with a logic operation section 5, a program counter 6, a stack pointer 7, a general-purpose register 8, and an external bus control section 9. The external bus control unit 9 is a circuit that controls input/output between the internal bus 10 and the address bus 3 and data bus 4. Here, when the logical operation unit 5 accesses the external memory 2, the address is output from the program counter 6, stack pointer 7, or general-purpose register 8. Accessing by the address indicated by the program counter 6 is called an instruction fetch, accessing by the address indicated by the general register 8 is called a data read/write, and accessing by the address indicated by the stack pointer 7 is called a stack push/pop. I'm calling. FIG. 3 shows an explanatory diagram of the memory address space of the external memory 2 shown in FIG. 2, which is accessed in this manner.

As shown in the figure, the memory address space is set to 0.
Assume that the width is set to 000 to FFFF. in this case,
Programs are stored, for example, at addresses 2000 to 3000, and data are stored at addresses 8000 to 9000. Also, the stack data is another 6000
It is stored at addresses ~6500. Therefore, when the microprocessor 1 accesses such an address space 18, it must first call a program, perform a predetermined calculation process, store the result as data, and temporarily hold it during the calculation. Processing such as writing the stack data to memory is performed. In this way, the program, stack data, and data are stored in completely different address spaces, so a set of address buses 3
If access is performed using the data bus 4 and the data bus 4, the locality and continuity of addresses will be reduced.

[0005] Address locality refers to the property that a part of the address space is accessed continuously. If a concentrated area is accessed continuously, address signals can normally be generated at high speed and high-speed access is possible. For example, an access in which only the lower several bits of a 16-bit address signal change can be performed at extremely high speed. Furthermore, if there is continuity such that the address is simply incremented or decremented, even faster access becomes possible.

However, when performing the above-mentioned arithmetic processing, if the program and data are accessed alternately, such high-speed processing will be hindered. FIG. 4 shows a block diagram of another conventional device in which instruction access and data access are performed via separate buses in order to solve the above problems. The microprocessor 1-2 shown in the figure has a logic operation unit 5 similar to the microprocessor 1-1 shown in FIG.
, a program counter 6, a stack pointer 7, and a general-purpose register 8. And these and internal bus 1
The instruction bus control section 11 and the data bus control section 12 are connected through the bus control section 0. The instruction bus control section 11 is connected to the instruction memory 13 via an instruction bus 15. Further, the data bus control unit 12 is connected to the data memory 14 via a data bus 16.

Microprocessor 1-2 having the above configuration
For instruction fetch accessed using the program counter 6, the instruction memory 13 is accessed exclusively via the instruction bus 15. Data read/write by the general-purpose register 8 and stack push/pop by the stack pointer 7 are performed by the data memory 14 via the data bus control unit 12 and the data bus 16.
access to. As a result, access to programs and access to data are performed using separate instruction buses.
5 and the data bus 16, it is possible to improve the locality and continuity of addresses as described above.

FIG. 5 shows a memory access operation diagram comparing the device shown in FIG. 2 and the device shown in FIG. 4. Figure 5 (a
) illustrates the address signals appearing on the address bus 3 shown in FIG. 2 and their operations. As shown in the figure, in the case of the device in FIG. 2, for example, the program at address 2000 is read and
Processing in which the address signal is frequently switched is executed, such as writing data to address 00, then reading the program at address 2001, and writing data to address 8005. On the other hand, in the device shown in FIG.
As shown in (b) and (c), the instruction bus is 2000
Read the address command, then 2001, 2002, 20
Instructions at consecutive addresses such as 03 are read in order. On the other hand, regarding the data bus, data write access is performed to relatively narrow areas such as writing to address 8000, addresses 8005 and 8003, and so on. Conventionally, this has been done to improve the access speed of the external memory by the microprocessor.

[0009]

By the way, even with the configuration shown in FIG. 4, the data stored in the data memory and the stack data are stored in relatively separate areas in the address space. Ru. Therefore, if reading/writing data and pushing/hopping stack data are frequently performed alternately, the same problem of reduced access speed as already explained with reference to FIG. 2 occurs.

In order to solve this problem, it is conceivable to further divide the data bus control section into two, one for stack data and one for normal data, and provide dedicated buses for each. However, in such a configuration, the number of bus signal lines increases three times as much as in the example shown in FIG.
This becomes an obstacle to the miniaturization of microprocessors, and new problems arise in wiring and mounting methods. The present invention has been made by focusing on the above-mentioned points.
The object of the present invention is to provide a stack control device that improves the continuity and locality of access addresses and speeds up the operation of a microprocessor while preventing an increase in price.

[0011]

[Means for Solving the Problems] A stack control device of the present invention includes a processor that executes arithmetic processing, an external memory that is connected to the processor via a bus line and that is accessed when the processor executes the arithmetic processing. a bidirectional buffer that stores stack data when the processor executes stack processing; and a bidirectional buffer that stores the stack data in order to operate the bidirectional buffer;
a buffer memory control unit that stores the stack data in a first-in, last-out manner, and controls the stack data to be retrieved in a first-in, first-out manner when stack data exceeding the capacity of the bidirectional buffer is to be stored in the bidirectional buffer; When the stack data is retrieved from the bidirectional buffer in a first-in, first-out manner, the stack data is written to the external memory via the bus line, and the stack data is read from the bidirectional buffer and stored in the bidirectional buffer. The device is characterized by comprising a stack pointer that reads the stack data from the external memory and returns it to the bidirectional buffer when the stored stack data is about to become less than its capacity.

0012

[Operation] This device is equipped with a bidirectional buffer capable of first-in, last-out operation and first-in, first-out operation. The stack data is stored in this bidirectional buffer, and as long as the capacity of the bidirectional buffer allows, stack data is not stored in the data memory. Therefore, the data bus is used exclusively for data access. On the other hand, when stack data exceeding the capacity of the bidirectional buffer is generated, the stack pointer operates for the first time, and the stack data pushed out from the bidirectional buffer is stored in the data memory. When the stack data stored in the bidirectional buffer decreases, the stack data is read out from the data memory again and returned to the bidirectional buffer. This reduces the degree to which stack data is accessed via the data bus and speeds up access.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained in detail below using examples shown in the drawings. FIG. 1 is a block diagram showing an embodiment of the stack control device of the present invention. This device consists of a microprocessor 2
0 is connected to the instruction memory 13 via the instruction bus 15 and connected to the data memory 14 via the data bus 16. The microprocessor 20 is provided with a logic operation section 5, a program counter 6, a general-purpose register 8, a stack pointer 21, a bidirectional buffer 22, a buffer memory control section 23, an instruction bus control section 11, and a data bus control section 12. ing. Further, these are interconnected via an internal bus 10. The configurations of the logic operation unit 5, program counter 6, general-purpose register 8, instruction bus control unit 11, and data bus control unit 12 included in the microprocessor 20 are already shown in FIGS. 2 and 4.
There is no difference from the circuit block of the conventional device explained by. Furthermore, the configurations of the control memory 13, data memory 14, command bus 15, and data bus 16 are also the same as in the conventional device.

Here, the microprocessor 20 of the present invention
The bidirectional buffer 22 and the buffer memory control unit 23
It is distinctive in that it has been added. This bidirectional buffer 22
The buffer memory controller 23 provides two functions to a normal buffer memory: a function to store data in a first-in, last-out manner, and a function to store data in a first-in, first-out manner. That is, when the bidirectional buffer 22 is used to store stack data, the stack data is used on a first-in, last-out basis. However, if the stored stack data exceeds the capacity of the bidirectional buffer 22, the oldest stored stack data is pushed out of the bidirectional buffer 22, and this is transferred to the data memory 14.
Perform actions such as being evacuated. Therefore, in this case, the bidirectional buffer 22 is configured to function as a first-in, first-out memory.

The buffer memory control unit 23 is composed of a counter and a gate circuit that output various control signals for performing the above operations. The configuration of the stack pointer 21 itself is the same as that of a conventional stack pointer, but the conventional stack pointer accepts push and pop instructions from the logic operation unit 5 and immediately transfers the write address and read address to the data memory 14. It was outputting to. In contrast, the stack pointer 21 used in the present invention is configured to operate under the control of the buffer memory control section 23 only when the stack data stored in the bidirectional buffer 22 overflows.

FIG. 6 shows a detailed operational diagram of the apparatus of the present invention. (a) to (e) in FIG. 6 show the case where the stack data is operating at less than the capacity of the bidirectional buffer. The left side of the figure shows the access contents of the logic operation unit, and the center shows the state of the bidirectional buffer. The right side shows the contents of access to the data memory 14, and the right side shows the contents of the stack pointer 21. For example, when there is a push command for stack data d1 from the logic operation unit 5 in FIG. 1, the data is stored in the bidirectional buffer 22 [FIG. 6(a)]. Then, when the logic operation unit 5 issues a push command for the stack data d2,
This data is also stored in the bidirectional buffer 22 [Fig.
b)]. Similarly, if there is another push command for stack data d3, this is also stored in the bidirectional buffer 22 [
Figure 6(c)]. Next, when a pop instruction is issued from the logic operation unit 5, the stack data d3 stored most recently is read out from the bidirectional buffer 22 [FIG. 6(d)]. Similarly, when a pop instruction is input again, the stack data d stored in the bidirectional buffer 22 most recently
2 is read out [FIG. 6(e)]. During this time, there is no access to the data memory 14 shown in FIG. 1, and the stack pointer 21 does not operate, with its contents set to P0.

FIGS. 6(f) to 6(j) show an example in which the bidirectional buffer 22 stores stack data exceeding its capacity. In FIGS. 6F and 6G, it is assumed that push commands for stack data dn-1 and dn are input successively. Assume that the capacity of the bidirectional buffer 22 is equivalent to n pieces of stack data. In this case, in Figure 6 (
In the state shown in g), the bidirectional buffer 22 becomes full.

Therefore, as shown in FIG. 6(h), when there is a push command for stack data dn+1 again,
As it is, it cannot accommodate all the stack data. At this time, the bidirectional buffer 22 first stores stack data dn+1 that is input last, while pushing out stack data d1 that is stored first in a first-in, first-out manner. At this time, the stack pointer 21 operates and outputs the address Px-1 for storing the stack data to the address bus of the data bus 16 through the internal bus 10 and data bus control unit 12 shown in FIG. As a result, the data memory 14 accepts the stack data d1 and stores the stack data at the corresponding address. In FIG. 6(i), furthermore, stack data dn+2
In this case, the stack data d2 is further pushed out, and the stack data d2 is stored in the corresponding location of the data memory 14 according to the address Px-2 generated by the stack pointer.

Next, in FIG. 6(j), the logic operation section 5
If there is a pop instruction from , the stack data dn+2 stored most recently is read from the bidirectional buffer 22. On the other hand, in the bidirectional buffer 22, one space becomes available due to the reading. Therefore, the stack pointer 21 generates the address Px-1 and reads the stack data d2 stored in the data memory 14. This stack data is then stored in the bidirectional buffer 22. The device configured as above is shown in FIGS. 6(a) to (e).
If the capacity of the bidirectional buffer 22 is set so that most of the operations are as shown in FIG.

If the amount of stack data generated in arithmetic processing is known in advance, the capacity of the bidirectional buffer 22 can be set to be greater than the amount of stack data generated as long as the amount is appropriate. In other words, there is no need to use the data bus 16 for stack data access at all. However, the contents of the arithmetic processing executed by the logic operation unit 5 are unknown, and the degree of freedom of the calculation must not be restricted. Therefore, if the bidirectional buffer 22 is selected to have a realistic capacity, and even if there is stack data exceeding that capacity, it is possible to push that amount to the data memory 14, the logic operation section 5 can be Conventional operations can be performed without being aware of the existence of the buffer 22 at all.

In order to perform the above operations, the buffer memory control unit 23 performs processing to generate signals as shown in FIGS. 7 to 10. Figure 7 shows
FIG. 7 is an explanatory diagram of an operation when a push command is performed below the bidirectional buffer capacity. As shown in the figure, when a push instruction for storing stack data is output from the logic operation unit to the bidirectional buffer 22, a write enable signal is input to the bidirectional buffer 22 according to the push instruction, and the stack data is stored in the bidirectional buffer 22. Writing is performed.

FIG. 8 is an explanatory diagram of the operation in a pop instruction whose capacity is less than the capacity of the bidirectional buffer. As shown in the figure, when a pop instruction is output from the logic operation unit 5, a read enable signal is input to the bidirectional buffer 22, and the stack data is read out. The operations shown in FIGS. 7 and 8 as described above show a state in which the bidirectional buffer operates on a first-in, first-out basis. On the other hand, FIG. 9 is an explanatory diagram of the operation when a push command exceeds the capacity of the bidirectional buffer. In this state, stack data is pushed out from the bidirectional buffer 22 in a first-in, first-out manner. In this case, when a push command is output from the logic operation unit 5, a write enable signal is input to the bidirectional buffer 22, and stack data is written. On the other hand,
From the buffer memory control unit 23, the bidirectional buffer 22
A read enable signal is output to the bidirectional buffer 22, and stack data is read out from the bidirectional buffer 22 in a first-in, first-out manner. Further, a push command is output from the buffer memory control unit 23 to the stack pointer 21, and the stack pointer 21 generates a write address. This write address is input to the data memory 14, and stack data is written to that address.

FIG. 10 is a diagram illustrating the operation when a pop instruction exceeds the capacity of the bidirectional buffer. As shown in the figure, when a pop instruction is output from the logic operation unit 5, the bidirectional buffer 22
A read enable signal is input to the bidirectional buffer 2.
Stack data is read from 2. At this time, a pop instruction is sent from the buffer memory control unit 23 to the stack pointer 2.
1, and the stack pointer 21 outputs the read address to the data memory 14. As a result, the stack data is read from the data memory 14, and at the same time, a write enable signal is input from the buffer memory control section 23 to the bidirectional buffer 22. As a result, the stack data read from the data memory 14 is written into the bidirectional buffer 22.

The buffer memory control section 23 operates to generate write enable signals, read enable signals, push commands, pop commands, etc. as shown in FIGS. 7 to 10, and output them to each section. This operation can be easily realized using well-known counters and gate circuits. Stack push is usually used to hold the return address when a subroutine is called or data to be passed to a subroutine, etc. Pushed data is likely to be popped in a relatively short time, and a large amount of data is pushed continuously. The possibility of it happening is small. Therefore, by appropriately selecting the size of the bidirectional buffer as described above, it is possible to significantly reduce the frequency of accessing the data memory by stack push/pop.

[0025]

According to the stack control device of the present invention described above, stack data is stored in a bidirectional buffer, and when stack data is generated within the capacity of the bidirectional buffer, stack push/pop is performed. External memory access is not performed. For this reason, locality and continuity of external memory access can be improved, and processing speed can be increased. In the above embodiment, an example was shown in which the microprocessor and external memory were connected via an instruction bus and a data bus. It is possible to implement the present invention in the same way even for those in which there are three or more types. Furthermore, when stack push/pop is performed only on bidirectional buffers, faster access is possible than when accessing external memory. From this point of view as well, it can be said that the effect of increasing the processing speed of a microprocessor by the stack control device of the present invention is high.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a stack control device of the present invention.

FIG. 2 is a block diagram of a conventional device.

FIG. 3 is an explanatory diagram of a memory address space of an external memory.

FIG. 4 is a block diagram of another conventional device.

FIG. 5 is an explanatory diagram of memory access operation.

FIG. 6 is an explanatory diagram of the operation of the apparatus of the present invention.

FIG. 7 is an explanatory diagram of push command operation below the bidirectional buffer capacity.

FIG. 8 is an explanatory diagram of pop instruction operation below the bidirectional buffer capacity.

FIG. 9 is an explanatory diagram of push command operation exceeding the bidirectional buffer capacity.

FIG. 10 is an explanatory diagram of the operation of a pop instruction that exceeds the bidirectional buffer capacity.

[Explanation of symbols]

5 Logic operation section 6 Program counter 8 General purpose register 11 Instruction bus control unit 12 Data bus control section 13 Instruction memory 14 Data memory 15 Instruction bus 16 Data bus 20 Microprocessor 21 Stack pointer 22 Bidirectional buffer 23 Buffer memory control unit

Claims (1)

[Claims] 1. A processor that executes arithmetic processing, an external memory that is connected to the processor via a bus line and is accessed when the processor executes the arithmetic processing, and stores stack data when the processor executes the stack processing. In order to operate this bidirectional buffer, the stack data is stored in the bidirectional buffer in a first-in, last-out manner, and stack data exceeding the capacity of the bidirectional buffer is stored in both of the bidirectional buffers. When the stack data is to be stored in the bidirectional buffer, the stack data is extracted from the bidirectional buffer in a first-in, first-out manner; When the stack data is read from the bidirectional buffer and the stack data stored in the bidirectional buffer is about to become less than its capacity, the stack data is read from the external memory via the external memory. A stack control device comprising: a stack pointer that reads data and returns it to a bidirectional buffer.