JPS62165795A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To attain high speed reading and the decision of depth of write by providing two sense amplifies of static type and dynamic type as sense amplifiers receiving a read voltage of a memory array. CONSTITUTION:A precharge MOSFET Q16 is provided to apply read operation of dynamic system to a common data line CD of a memory array M-ARY, an inverting operation mode signal uh and a precharge signal phip are fed to the gate and the FET Q16 is turned on by the signal phip only at the read by the dynamic system to precharge a data line CD. On the other hand, a reference voltage Vr from a connecting point between MOSFETs Q24 and Q23 is fed to a gate of a MOSFET Q18 and in reading the MOSFETs Q17, Q18 at the static mode, an OR signal between the precharge signal phip an the operating mode signal uh is fed to the gate of the precharge MOSFET Q24.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device, for example,
The present invention relates to a technology that is effective when used in an EFROM (Electrically Programmable Read Only Memory) device that uses FAMO3 (Floating Gate Avalanche Injection Insulated Gate Field Effect Transistor) as a storage element (memory cell).

[Conventional technology]

An EFROM device that uses a semiconductor element such as FAMO3 (floating avalanche injection MOS FET) as a memory element (memory cell) is known (
For example, see Japanese Unexamined Patent Publication No. 152933/1983). F.A.
The MO3) transistor is made to have a high or low threshold voltage with respect to the selection level of the word line coupled to its gate by its write operation.

That is, the FAMO3) transistor is changed from a low threshold voltage to a high threshold voltage by writing.

[Problem that the invention seeks to solve]

The selection level of the word line to which the control gate of the FAMO3 transistor is connected increases as the operating power supply voltage Vcc rises. This fact can be used to determine the amount of writing. That is, when a static type sense amplifier is used, as shown in FIG. 2, the determination level Vr increases as the power supply voltage Vcc rises, so the potential of the word line is increased by increasing the power supply voltage Vcc. This can be indirectly determined from the reversal of the read level due to the FAMOS transistor switching from the off state to the on state AH when AH exceeds the above-mentioned high threshold voltage. As a result, the power supply voltage Vcc (la
The amount of information written in the FAMOS transistor can be determined from x). However, when a static sense amplifier is used, the amount of signal change between the read high level H and low level L becomes large with respect to the judgment level Vr, so the operating speed becomes slower. .

Therefore, it is conceivable to use a dynamic sense amplifier to speed up the read operation, but in this case, it becomes impossible to identify the write H. This is because, as shown in Figure 3, the dynamic sense amplifier has a precharge level selected by the FAMOS.
The voltage difference is amplified by discharging the current of the transistor and the current of the Gummy-FAMO3) transistor, which has a conductance that is about half that of a FAMOS transistor, which has a low threshold voltage, for example. For this reason, when the operating voltage is increased as shown in Figure 4, the FAMOS has a high threshold voltage.
Read high level H depending on the on state of the transistor
However, the dummy FAMO decreases according to the above voltage increase.
3) Since the current in the transistor also increases, a high level read level is not determined to be a low level due to an increase in the operating voltage VCC, unlike when the static type sense amplifier is used. As a result, when using a dynamic sense amplifier, high-speed operation can be achieved, but on the other hand,
Since the amount of written information (writing depth) cannot be measured, a problem arises in terms of reliability.

An object of the present invention is to provide a semiconductor memory device that operates faster and has improved reliability.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, two sense amplifiers, a static type and a dynamic type, whose substantial amplification operations are controlled in a complementary manner according to a predetermined operation mode control signal, are provided as sense amplifiers that receive the read voltage of the memory array.

[For production]

According to the above-mentioned means, during a normal read operation, the dynamic type sense amplifier can be activated to perform high-speed reading, and in data retention evaluation, the static type sense amplifier can be activated and the readout can be performed at high speed. Writing depth can be determined.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of a memory array section when the present invention is applied to an EPROM device.

Although not particularly limited, each circuit element in the figure may be a known CM.
With O3 (complementary MO3) integrated circuit manufacturing technology, 1
formed on a semiconductor substrate such as single crystal silicon.

Although not particularly limited, the integrated circuit is formed on a semiconductor substrate made of single-crystal P-type silicon. N channel M
The OS FET is made of polysilicon formed on the surface of the semiconductor substrate with a source region and a drain region formed on the surface of the semiconductor Ts plate, and a thin gate insulating film formed on the surface of the semiconductor substrate between the source region and the drain region. It consists of a gate electric bridge that looks like this. The P-channel MO3FET is formed in an N-type well region formed on the surface of the semiconductor substrate.

Thereby, the semiconductor substrate constitutes a common substrate gate for a plurality of N-channel MOS FETs formed thereon. The N-type well region constitutes a substrate cage for the P-channel MOS FET formed thereon. P
The substrate gate of the channel MOS FET, ie, the N-type well region, is coupled to the power supply terminal Vcc of FIG.

Although not particularly limited, the EFROM device of this embodiment includes:
X supplied from an external terminal (not shown).

A complementary address signal formed through an address buffer receiving a Y address signal (not shown) is supplied to an address decoder DCR. In the figure, the address buffer and address decoder are in the same circuit block XADB-D.
CR, YADB-DCR, respectively. Although not particularly uniform, the above address buffer XADB
, YADB is activated by an internal chip selection signal ce, takes in an address signal from an external terminal, and generates a complementary address signal consisting of an internal address signal in phase with the address signal supplied from the external terminal and an address signal in opposite phase. Form.

Address decoder DCR(X) forms a selection signal for word biw of memory array M-ARY according to its complementary address signal.

Address decoder DCR(Y) forms a selection signal for the data line of memory array M-ARY according to its complementary address signal.

The above-mentioned memory array M-ARY includes a plurality of representative FAMO3) registers (non-volatile memory elements, MOS FETQ1 to Q6), word lines Wl, W2, and data lines D1 to D1. )n. In memory array M-ARY, FAMO3! arranged in the same row! - transistors Q1 to Q3 (Q4
~Q6) are connected to the corresponding word lines Wl (V/2), respectively, and the FAMOS transistors Ql, Q4~Q3 . The drains of Q6 are connected to corresponding data lines D1 to Dn, respectively. The common source line C3 of the FAMOS transistors is grounded, although not particularly limited thereto.

Each of the data lines D1 to Dn is connected to the address decoder D.
It is connected to the common data &;ICD through column selection switches ioSFETQ7-Q9 which receive the selection signal formed by CR(Y). Each of the 0 or more MOS FETs connected to the common data line CD is an output terminal of a data input circuit DIB for writing that receives a write signal input from an external terminal I10, and each of the MOS FETs is composed of an N-channel MOS FET. There is.

The following two sense amplifiers are provided for the common data ill CD. One of them is a static sense amplifier used for data tension evaluation, and is composed of the following circuit elements. In addition, the common data line CD is equipped with a precharge MOS in order to realize a read operation using a tie-limiter method, which will be described later.
FET Q 16 is provided. This MOS F
The gate of E T Q 16 is connected to an AND signal (uh・
φp) is supplied. As a result, the precharge MO3FET Q16 is turned on in accordance with the precharge signal φp only during a read operation using the dyna capture/seven resetting method as described later, and performs a precharge operation on the common data line CD.

The common data line CD has an N-channel switch MO3FETQ controlled by the operation mode signal Uh.
An N-channel type amplifying MO3FET QIL is provided, the sources of which are connected via 25. This amplification MO
Between the drain of the 3FETQ11 and the t source voltage terminal Vcc, there is a P-ray channel type negative raTMos FETQl.
2 is provided. The above negative 7tijMO3FE'r"Q
Step 12: An operation is performed in which a bridge current is applied to the common data '#ACD for a read operation.

In order to increase the sensitivity of the amplification MO3FETQII, the common data line C is connected via the switch MO5FETQ25.
The voltage of D is the N-channel drive MO3FETQ13.
The drive MOS F' which is the human power of the inverting amplifier circuit consisting of
Supplied to the gate of E'l'Q l 3. The voltage of this inverting amplifier circuit is supplied to the gate of the amplifying MO3FETQ11. In general, in order to prevent wasteful consumption of current between non-operating M of the sense amplifier, the amplification MO
An N-channel MO3FET QI 5 is provided between the gate of the 3FET QI 1 and the ground potential point of the circuit.

This MO3FETQI 5 and the above P channel MO3F
The gates of the ETQ14 are commonly supplied with the sense amplifier operation timing control signal π.

In the data retention evaluation mode, the sense amplifier operation timing signal SC is set to low level, and the MO3F
ETQI 4 is turned on and MO3FETQ15 is turned off. and address decoder X-DCR,
The memory cell selected by Y-DCR has a threshold voltage higher or lower than the word line selection level, depending on the write data.

, ] If the selected memory cell is turned off regardless of the word line selection level, the common data line CD is brought to a relatively high level by the current supplied from MO3FETs QI2 and Qll.

On the other hand, when the selected memory cell is turned on by the word line selection level, the common data line CD is set to a relatively low level.

The MO3FETQI 1 for amplification performs an amplification operation of the gate-grounded source input, and transmits its output signal to the next differential amplifier circuit via the N-channel switch MO3FETQ26 controlled by the control signal uh. It will be done.

The other one used for normal read operations is a dynamic sense amplifier, which is composed of the following circuit elements.

The signal on the common data line CD is
The differential M
Supplied to the gate bridge of O5FETQI7. Differential MO3FETQI is not paired with this differential MO5FETQ17.
The dummy FAMO3 connected in series is connected to the gate of No.8.
F-run transistors Qdl and Qd2, dummy column switch MO3FETQ23, and precharge MO5FET
It is coupled to a reference voltage generation circuit composed of Q24.

That is, the gate l- of the MOS FET Q18 is supplied with the reference voltage r obtained from the connection point of the MOS FETQ24 and Q23.In this embodiment, the differential voltage In order to cause MO3FETQI 7.Ql 8 to perform a static differential amplification operation during a read operation in static mode, the gate of the precharge MO3FET Q24 is connected to the precharge signal φp and the operation mode signal uh. OR signal (
uh+φp) is supplied.

A power switch MOS FET Q19 is provided between the common source of the differential MO3FETs QI7 and Ql8 and the ground potential point of the circuit to control the operation timing thereof. A sense amplifier operation timing signal sac is supplied to the gate of this power switch MO3FETQ19.

In addition, the drains of the differential MO3FETs Q17 and Ql8(7) are provided with P-channel MO3I"ETs Q2o and Q21 in a current mirror configuration as active load circuits, although this is not particularly limited.

The output signal of this differential amplifier circuit is the data output circuit DOB.
The signal is sent from the external terminal I10 via the external terminal I10.

The control circuit C0NT is a chip enable signal supplied to external terminals CE, OE, PGM, and vpp.

Output enable signal, program signal, high voltage for writing, and internally generated A
In response to the TD (address signal change detection) signal, internal control signals ce, 7-9-f, sac, uh, uh and φp are activated.
timing signals such as, and low voltage for reading Vcc/high voltage for writing selectively supplied to the address decoder.
Form pp etc. For example, chip enable signal CE
is low level, output enable signal OE is high level, and program signal PGM is low level, then
The write mode is set, and the seven internal signals are set to low level and CO is set to high level. The high voltage Vl)IJ is supplied to the address decoder circuits XDCR, YDCR and the data input circuit DIB.

Also, if the chip enable signal CE is low level, the output enable signal OE is low level, the program signal PGM is high level, and Vl)p is a high voltage for writing, the verify mode is entered, and the above internal signals 7 and C
8 is set to high level.

In this verify mode, each circuit XDCR, YDCR
and DrB, whose operating voltage is the above-mentioned high voltage Vl'lp.
It is switched and supplied like the power supply voltage VCC from .

Furthermore, if the chip enable signal CB is at low level, the output enable word OE is at low level, the program signal PGM is at high level, and Vpp is a low voltage for reading (same level as cc), the read mode is set, and the above-mentioned internal Signal ma τ and c.

is raised to a high level.

In addition, the control circuit C0NT has an itt source voltage Vcc of about 6
(2) includes a voltage detection circuit that identifies whether or not the voltage is higher than the above, and when the power supply voltage Vcc is lower than the voltage, the inverted uh signal is set to high level and the non-inverted uh times signal is set to low level; In this case, the inverted ujx (No. 8) is set to low level, the non-inverted Uh signal is set to high level, and the signal 〒7 is set to low level.

In a normal read operation, the power supply voltage Vcc is not set to a high voltage as mentioned above, so the above-mentioned inverted u
The high level of the h-fold signal turns MO3FETQ22 on, and the low level of the non-inverted uh-fold signal turns MO3FETQ22 on.
FET Q25 and Q2G are turned off. Further, since the seven signals are set to high level, the static type sense amplifier is placed in a non-operating state.

In this state, the common data line CD and the reference voltage generation circuit are precharged in accordance with the precharge signal φp prior to reading out the memory cell. If the selected FAMO3) transistor is in an off state, the potential of the common data line remains at a high level, and if it is in an on state, it is discharged to a low level. In sync with this,
The reference voltage Vr of the reference voltage generation circuit is set to a dummy FAM.
O3) Discharge is performed by transistors Qdl and Qd2. The above two potential difference is the differential MO3FETQ
17 and C18, and is transmitted to the data output circuit DOB.

When evaluating the write amount of the FAMoS transistor, the power supply voltage Vcc is set to a high voltage of about 6 V or more. In response, the inverted uh times signal is set to low level and the non-inverted uh times signal is set to high level. As a result, the switch MO3FETQ22 is turned off, and the switches MO3FETQ25 and C26 are turned on. Moreover, the precharge MO3FET Q16 provided on the common data line CD is turned off by the above-mentioned inverted low level of 11 h <7'E. On the other hand, the precharge MOS FETQ of the reference voltage generation circuit
24 is kept on by the high level of the non-inverted uh signal. Thereby, the reference voltage Vr is set to a voltage according to the conductance ratio of the MO3FETQ24 and the MOS FETQ23 or Gummy-FAMO3 transistor.

Therefore, the potential of the common data 'aCD is MO
The level is set according to the conductance ratio of the 3FETQI L load MO3FETQI 3 and the selected FAMOS transistor, and the level is amplified and transmitted to the differential amplifier circuit. In this case, the potential of the common data line CD is
As the voltage Bt voltage Vcc rises, the selection level of the word line rises, thereby turning off the FAMOS transistor which has been made to have a high threshold voltage by the write operation. As a result, the potential of the common data line CD is lowered to a low level by the supply of the increased voltage 'a' Vcc. With such an increase in the power supply voltage Vcc, the power supply voltage VCC when the output of the differential amplifier circuit is reversed.
From 1. The writing depth of the F AMOS ) transistor, in other words the increased threshold voltage, can be determined.

The effects obtained from the above embodiments are as follows. In other words, (1) High-speed reading is possible by providing a static sense amplifier and a dynamic sense amplifier to perform a dynamic sensing operation during normal read operations, and using static sense amplifiers during write evaluation. The effect is that the amount of writing can be determined by the sense operation of the method.

(2) By keeping the precharge MOS FET of the reference voltage generation circuit of the differential amplifier circuit in the on state during static sensing operation and operating it as a load MO9FET, it is possible to re-operate the dynamic and static sensing methods. Available. This provides the effect that the circuit can be made into a cylindrical element while providing the above two functions.

(3) By detecting the voltage level of the power supply voltage Vcc and switching between the static and dynamic sensing operations described above, normal reading and writing evaluation can be performed automatically without increasing the number of external terminals. You can get the effect that you can.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in FIG. 1, it is preferable to supply the output signal of the amplified MO3FET QII to the CMOS inverter circuit and use its logic threshold voltage to determine high level/low level. In this case, the output signal of the CMOS inverter circuit may be selectively transmitted to the data output circuit DOB according to the signal uh. Further, the above-mentioned sense type replacement may be formed from a combination of control signals supplied from external terminals, or may be formed by providing an independent control terminal.

Furthermore, in an EPROM device that writes/reads memory data consisting of multiple points in parallel, it is necessary to provide the memory array M-ARY shown in FIG. It can be configured by

In the above explanation, the invention made by the inventor of the present application was mainly applied to an EPROM device, which is the background technical field, but the invention is not limited to this, and the relatively high E E P P using a memory element that has a threshold voltage or a low threshold voltage, such as a mask ROM or a memory element such as MNOS (Metal Nitride Oxide Semiconductor) , OM, and other semiconductor memory devices, and these memory circuits are
It may be built into a digital integrated circuit such as a one-chip microcomputer.

[Efficacy of invention]

Effects obtained by typical inventions disclosed in the present application -'c' a A simple explanation will be as follows. That is, by providing two sense amplifiers of a static type and a dynamic type, the dynamic type can realize high-speed normal readout, and the static type can evaluate the amount of prediction.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of an EPROM device to which the present invention is applied, FIG. 2 is a voltage characteristic diagram for explaining sensing operation using the static method, and FIG. 3 is a diagram of normal operating voltage. An operation waveform diagram for explaining the operation of the sense amplifier according to the original dynamic method. FIG. 4 is an operation waveform diagram for explaining the operation of the sense amplifier according to the original dynamic method of high voltage operation.

Claims (1)

[Scope of Claims] 1. A memory element configured in a matrix arrangement, which has a threshold voltage higher or lower than a selected level of a word line coupled to a gate according to stored information. and two sense amplifiers, a static type and a dynamic type, whose substantial amplification operations are complementarily controlled in accordance with a predetermined operation mode control signal in response to the read voltage of the memory array. Semiconductor storage device. 2. The memory elements constituting the memory array are FAMO
2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is an S transistor.