JPH01243294A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To perform the readout of a memory element at high speed by forming a precharge voltage set with high accuracy in the neighborhood of the operating point of a sense amplifier. CONSTITUTION:In a precharge circuit, a FETQ19 is turned on by the 'L' of a precharge signal, the inverse of PC, and inversion amplifier circuits (Q18 and Q19) which set the FET as a load are set at operating states. A voltage shifted by the threshold value of a Q20 from an intermediate voltage decided by a conductance ratio of the Q18 to the Q19 is transmitted to data lines D via switches (Q14-Q17) between a precharge line PL and the data lines, and precharges respective data line. When the data line D to which a selected memory cell is coupled is coupled with a common data line CD, the initial stage circuit PA of the sense amplifier SA is precharged in the neighborhood of the operating point of the sense amplifier, and a signal corresponding to the ON and OFF states of the memory cell is sent to the sense amplifier via the line D and the line CD, and since the amplifier outputs an amplifier signal immediately by a signal, the inverse of SC, the readout is performed at high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, for example, an EPROM (erasable & programmable memory device) using a non-volatile memory element having a stacked gate structure that is electrically writable. This relates to technology that is effective for use in read-only memory (read-only memory).

[Conventional technology]

The precharge circuit provided in the data line to which the nonvolatile memory element is connected is one that performs precharging with a full precharge voltage such as the power supply voltage, or one that lowers the level by the threshold voltage of the MOSFET from the power supply voltage. Generally, precharging is performed using a precharge voltage that has been set.

As an example of a precharge circuit, for example, Japanese Patent Application No. 62-0
There is No. 05979.

[Problem to be solved by the invention]

If the data line precharge level deviates from the sense amplifier's operating voltage point (the most sensitive bias voltage), memory with a relatively low threshold voltage is turned on relative to the word line selection level. In the read operation of the element, it takes time to discharge the precharge level of the data line by the storage element or the sense amplifier, and the read operation is delayed accordingly.

In addition, for high-speed readout, MOSFE
Even if you try to set the precharge voltage of the data line low by using the threshold voltage of T, the precharge MO
The precharge voltage fluctuates due to process variations in SFET.

Similarly, the operating voltage point of the MOS FET that constitutes the sense amplifier fluctuates due to process variations in the MOS FET.

Therefore, it is necessary to set the precharge voltage with a predetermined level margin, taking into account the worst case of process variations in the operating voltage point of the sense amplifier and process variations in the precharge MO3FET. has its limits.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device capable of speeding up read operations.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the operating voltage point of the sense amplifier is determined as a precharge circuit provided on a data line to which a memory element having a relatively high threshold voltage or a relatively low threshold voltage is connected according to stored information. A circuit similar to this circuit is used to form a precharge voltage corresponding to the vicinity of the operating voltage point of the sense amplifier.

[For production]

According to the above-described means, it is possible to form a precharge voltage set with relatively high accuracy near the operating voltage point of the sense amplifier, thereby enabling high-speed reading of the memory element.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of a memory array section when the present invention is applied to an EPROM device.

Although not particularly limited, each circuit element in the figure may be a known CM.
With O3 (complementary MO3) integrated circuit manufacturing technology, 1
formed on a semiconductor substrate such as single crystal silicon.

Although not particularly limited, the integrated circuit is formed on a semiconductor substrate made of single-crystal P-type silicon. N channel MOS
The FET is made of polysilicon, which has a source region, a drain region formed on the surface of the semiconductor substrate, and a thin gate insulating film formed on the surface of the semiconductor substrate between the source region and the drain region. Consists of a gate electrode. The P-channel MO3FET is formed in an N-type well region formed on the surface of the semiconductor substrate.

Thereby, the semiconductor substrate constitutes a common substrate gate of a plurality of N-channel MO3FETs formed thereon, and is coupled to a reference voltage terminal to which a ground potential of the circuit is applied. The N-type well region constitutes the substrate gate of the P-channel MO3FET formed thereon. The substrate gate or N-type well region of the P-channel MO3FET is coupled to the power supply terminal Vcc.

Although not particularly limited, the EPROM device of this embodiment includes:
X, Y address signals AX, AY supplied from external terminals
A complementary address signal formed through the receiving address buffer is supplied to the address decoder DCR. In the figure, an address buffer and an address decoder are shown as the same circuit blocks XADB-DCR and YADB-DCR, respectively. Although not particularly limited, the address buffers XADB and YADB are activated by an internal chip selection signal ce, take in address signals AX and AY from external terminals, and convert them into internal address signals that are in phase with the address signal supplied from the external terminals. A complementary address signal consisting of an address signal of opposite phase is formed.

Row (X) address decoder (X)DCR forms a selection signal for word line W of memory array M-ARY according to a complementary address signal of address buffer XADB.

Column (Y) address decoder (Y) DCR forms a selection signal for the data line of memory array M-ARY according to a complementary address signal of address buffer YADB.

The memory array M-ARY is typically 1
Two memory blocks are shown. This memory block consists of multiple MOS FETs each having a control gate and a floating gate, such as stacked gate transistors (non-volatile memory elements...MO3FETQ).
I to Q6), word lines WL W2 . . . and data lines D1 to Dn. In the memory block, the control gates of the stacked gate transistors Q1 to Q3 (Q4 to Q6) arranged in the same row are connected to the corresponding word line Wl (W2), and the control gates of the stacked gate transistors Q1 to Q3 (Q4 to Q6) arranged in the same row are connected to the corresponding word line Wl (W2), respectively. Ql, Q4-Q3. The drains of Q6 are connected to corresponding data lines D1 to Dn, respectively. The common source line C3 of the stacked gate transistors is grounded via a depletion type MO3FET QIO which receives the write signal we at its gate, although this is not particularly limited.

Although not particularly limited, in order to perform writing/reading in units of 8 bits, the memory array M-ARY is configured such that a total of 8 sets are provided. In the same figure,
One memory array M-ARY is shown as a representative example.

The conductance of the MO3FBTQIO is made relatively small by the low level of the internal control signal when writing. As a result, the potential of the common source line CS is made relatively high by making the conductance of MO3FET QIO relatively small. When the potential of this common source line C8 is made relatively high, the threshold voltage of the stacked gate transistor is made relatively high. Therefore, by supplying a high write voltage to the data line and making the word line unselected, the effective threshold voltage of the unselected stacked gate transistor is increased, so that the leakage current flowing therein can be reduced. . As a result, the write current supplied from the external terminal is efficiently supplied to the selected stacked gate transistor, making it possible to perform an efficient write operation. Note that during the read operation, the control signal wτ is The high level makes the conductance of MO3FETQIO relatively large, which increases the read speed.

Each of the data lines D1 to Dn constituting the one memory array M-ARY is connected to a common data line through column selection switches MO3FETQ7 to Q9 that receive a selection signal formed by the address decoder DCR(Y). Connected to CD.

A common data line CD is provided corresponding to each memory block. The common data line CD is connected to an output terminal of a write data input cover sofa DIB that receives a write signal input from an external terminal I10. Similarly, column selection circuit switches MO3FET similar to those described above are provided for other memory arrays M-ARY, and selection signals are generated by corresponding address decoders.

Each common data line CD provided corresponding to the memory array M-ARY is provided with a first stage amplifier circuit PA, which constitutes an input stage circuit of a sense amplifier and will be described next.

That is, in FIG. 1, the common data line CD illustratively shown above is provided with an N-channel amplification MO3FET Q11 whose source is connected. The drain of this amplification MO3FETQI 1 and the power supply voltage terminal V
A P-channel type load MO3FBTQI 2 to which a circuit ground potential is applied to its gate is provided between the MO3FBTQI2 and cc. The load MO3FET QI 2 operates to cause current to flow through the common data line CD for a read operation.

In order to increase the sensitivity of the above amplified MO3FETQI 1,
The voltage of the common data line CD is the voltage of the N-channel type drive MO.
3FETQ13 and P-channel type load MO3FETQ
The drive MO3 which is the input of the inverting amplifier circuit consisting of I4
Supplied to the gate of FETQI3. Also, an N-channel MO is connected between the common data line and the power supply voltage terminal Vcc.
3FETQI 7 is provided. The output voltage of this inverting amplifier circuit is
3FF.

Supplied to the gate of TQ17. Further, in order to prevent wasteful current consumption during the non-operation period of the sense amplifier, an N-channel MO3FET Q15 is provided between the gate of the amplification MO3FET QI 1 and the ground potential point of the circuit. This MO5FETQ15 and the above P channel MO
A sense amplifier operation timing signal τ is commonly supplied to the gates of the 3FETQI 4.

When reading a memory cell, the sense amplifier operation timing signal SC is set to low level, and the MO3FETQ
I4 is turned on and MOS FETQ15 is turned off. The memory cell has a threshold voltage higher or lower than the selected level of the word line, depending on the write data.

When the memory cell selected by each address decoder X-DCR, Y-DCR is turned off even though the word line is set to the selection level, the common data line CD is The potential is determined by the level limiter circuit, and the MO
3FETQ11 enters the cutoff state. On the other hand, when the selected memory cell is turned on by the word line selection level, the common data line CD is at a relatively low level, the output of the inverting amplifier circuit is at a relatively 1 level, and the current flows from MO3FETs Q17 and Qll. is supplied, and the common data line CDO low level is limited.

If the high level (level determined by the level limiter circuit) and low level of the common data line CD are limited, even though the common data line CD has capacitance such as stray capacitance that limits the signal change speed. It is possible to increase the speed of readout without any problem. That is, when data is read out from a plurality of memory cells one after another, the time required for one level of the common data line CD to change to the other level can be shortened.

In addition, the presence or absence of current flowing through MO3FETQI1 is determined by MO
Amplify with 3FETQ12 and send the output signal to CMOS
The information is transmitted to the amplifier circuit SA constituted by an inverter circuit. The output signal of this amplifier circuit SA is then sent to the corresponding data output buffer D.

Although not particularly limited, the signal is amplified by B and sent out from the external terminal I10. In addition, the external terminal I10
The write signal supplied from the data input cover sofa D
It is transmitted to the common data line CD via IB. Also between the common data line corresponding to the other memory blocks and the external terminal, a read circuit consisting of a sense amplifier and a data output buffer similar to the above, and a write circuit consisting of a data input cover sofa are provided, respectively.

The timing control circuit C0NT is connected to an external terminal CB.

Internal control signals ce, w according to the chip enable signal, output enable signal, program signal and high voltage for writing supplied to OE, PGM and Vl)I)
Timing signals such as e, SO, and pc, as well as read low voltage Vcc/write layer high voltage Vpp, etc., which are selectively supplied to the address decoder are formed.

In this embodiment, for high-speed reading, the data line D
The following precharge circuits are provided corresponding to 1 to Dn.

The precharge circuit utilizes a level limiter circuit in the sense amplifier to form a precharge voltage set near the operating voltage point of the sense amplifier. That is, the amplification MO3FETQI8 receiving the voltage of the precharge output line PL and the P-channel type load MO3F
It consists of an inverting amplifier circuit consisting of ETQI 9, and an N-channel precharge MO3FETQ20 whose gate is supplied with the output signal of this inverting amplifier circuit and which is provided between the precharge output line PL and the power supply voltage Vcc. . Note that the load MO3FET QI 9 has the precharge signal pc supplied to its gate, so that
It turns on only during precharge operation and acts as a load. By operating the inverting amplifier circuit using such a precharge signal T, the direct current consumed therein can be reduced.

The precharge output IPL is the precharge signal τ
P-channel type switch MO3FETQ21 that receives
.about.Q23 are coupled to data lines D1 to Dn, which are illustrated as representative data lines.

In the precharge circuit, the MO3FET Q19 is turned on by the low level of the precharge signal pc, and the inverting amplifier circuit using this as a load is put into operation. Therefore, an intermediate voltage similar to that of the level limiter circuit of the first stage circuit PA in the sense amplifier is generated on the precharge output line PL. In other words, from the intermediate voltage determined according to the conductance ratio of MO3FET QI8 and Q19, the MO3FET
The intermediate voltage is level-shifted by the threshold voltage of Q20. This intermediate voltage is applied to each data &'
This is transmitted to iD1 to Dn to perform their respective precharge operations. In this configuration, when the data line to which the selected memory cell is coupled is coupled to the common data line CD, the data line is precharged near the operating point of the sense amplifier. As a result, a signal corresponding to the on/off state of the sense amplifier is transmitted to the input of the sense amplifier through the data line and the common data line. Since the sense amplifier outputs an amplified signal immediately after starting the amplification operation in response to the low level of the timing signal sc, it is possible to realize a high-speed read operation.

As a circuit for forming the precharge voltage, a level limiter circuit provided in the first stage circuit of the sense amplifier and 84
The following circuit is used. In this configuration, MOS F
Even if there are process variations in ET, it is possible to form a precharge voltage that follows near the operating voltage point of the sense amplifier.

In other words, it becomes possible to accurately set the precharge level at the operating point where the sense amplifier has the highest sensitivity, so it becomes possible to stably perform high-speed reading of the memory element.

The effects obtained from the above examples are as follows. That is, (1) The operating voltage of the sense amplifier is used as a precharge circuit provided in a data line to which a memory element having a relatively high threshold voltage or a relatively low threshold voltage is connected according to stored information. A circuit similar to the circuit that determines the point is used to form a precharge voltage that corresponds to the vicinity of the operating voltage point of the sense amplifier. In this configuration, since the precharge voltage of the data line can be set with high accuracy near the operating voltage point of the sense amplifier, the effect of enabling high-speed reading of the memory element is obtained.

(2) As a sense amplifier, a level limiter is provided to limit the signal amplitude of the common data line, and a circuit similar to the level limiter circuit is used to form a precharge voltage of the data line. In combination with this effect, the effect of enabling high-speed reading is obtained.

(3) By forming the precharge voltage using a circuit similar to the circuit that determines the operating point of the sense amplifier, it is possible to achieve the effect of enabling high-speed readout that is not affected by process variations.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the read precharge circuit may be of any type as long as it is set near the operating voltage point with the highest sensitivity, depending on the specific configuration of the sense amplifier to be mounted. For example, when a differential amplifier circuit is used as the sense amplifier, the precharge voltage may be generated using a circuit similar to the voltage generating circuit that generates the reference voltage. In addition, when using a simple CMOS inverter circuit, a similar CM
The precharge voltage may be generated by short-circuiting the input and output of the OS inverter circuit.

In addition to the stacked gate structure non-volatile memory element described above, the memory element is an MNO memory element that can be electrically erased.
It may be an S (metal nitride oxide semiconductor) transistor or a FLOTOX (floating gate tunnel oxide) type. Alternatively, a mask type ROM whose threshold voltage can be changed by ion implantation or the like may be used.

The present invention can be widely used in semi-donor storage devices such as the above-mentioned EPROM, EEPROM, and mask type ROM, and may be built into a digital semiconductor integrated circuit device such as a microcomputer.

(Effects of the Invention) The effects obtained by typical inventions disclosed in this application are as follows.That is, depending on the stored information, a relatively high threshold voltage or a relatively low threshold voltage can be obtained. As a precharge circuit provided in the data line to which a memory element having a threshold voltage is coupled, a circuit similar to the circuit that determines the operating voltage point of the sense amplifier is used to precharge the voltage near the operating voltage point of the sense amplifier. By forming a precharge voltage corresponding to , it is possible to set the precharge voltage of the data line with high precision near the operating voltage point of the sense amplifier, thereby enabling high-speed reading of the memory element.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of an EPROM device to which the present invention is applied. XADB, YADB... address buffer, XDCR...
-X address decoder, YDCR...Y address decoder, M-ARY...memory array, PA...first stage amplifier circuit, SA...sense amplifier, DIR...data manual buffer, DOB...data output buffer, C0NT... timing control circuit

Claims (1)

[Claims] 1. A memory element configured to have a relatively high threshold voltage or a relatively low threshold voltage according to stored information, and a data line to which the memory element is coupled, It is characterized by including a precharge circuit that forms a precharge voltage using a circuit similar to a circuit that determines the operating voltage point of a sense amplifier that senses a read signal supplied from a storage element through a selected data line. semiconductor storage device. 2. The sense amplifier has an inverting amplifier circuit that receives a signal from the common data line to which the selected data line is coupled, and an output signal of the inverting amplifier circuit is supplied to the gate, and the gate is connected between the power supply voltage and the common data line. and an amplification MOSFET whose source is coupled to the common data line and whose drain outputs an amplified output signal, and the precharge voltage formed by the precharge circuit is 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is formed by a circuit similar to the level limiter circuit. 3. The semiconductor memory device according to claim 1, wherein the memory element is an electrically writable nonvolatile memory element having a stacked gate structure.