JPH0330238B2 - - Google Patents
Info
- Publication number
- JPH0330238B2 JPH0330238B2 JP11973787A JP11973787A JPH0330238B2 JP H0330238 B2 JPH0330238 B2 JP H0330238B2 JP 11973787 A JP11973787 A JP 11973787A JP 11973787 A JP11973787 A JP 11973787A JP H0330238 B2 JPH0330238 B2 JP H0330238B2
- Authority
- JP
- Japan
- Prior art keywords
- potential
- igfet
- logic
- word line
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000005669 field effect Effects 0.000 claims description 8
- 230000000295 complement effect Effects 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 4
- 230000015654 memory Effects 0.000 description 3
- 235000006040 Prunus persica var persica Nutrition 0.000 description 1
- 240000006413 Prunus persica var. persica Species 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
Description
【発明の詳細な説明】
本発明は信号線の駆動回路に係り、不揮発性半
導体メモリにおけるワード線の駆動回路に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal line drive circuit, and more particularly to a word line drive circuit in a nonvolatile semiconductor memory.
従来の不揮発性半導体メモリ素子を用いる半導
体記憶装置やプログラマブル・リード・オンリ・
メモリ（PROM）等は、エヌチヤネル（Ｎ−ch）
またはピーチヤネル（Ｐ−ch）型の絶縁ゲート
型電界効果トランジスタ（以下IGFET）つまり
単チヤンネル型IGFETにより構成される。 Semiconductor storage devices using conventional non-volatile semiconductor memory elements and programmable read-only devices
Memory (PROM) etc. are N-channel (N-ch)
Alternatively, it is constituted by a peach channel (P-ch) type insulated gate field effect transistor (hereinafter referred to as IGFET), that is, a single channel type IGFET.
しかし最近、省電力を図るために、不揮発性半
導体メモリのワード線の駆動回路を相補型
IGFET（CMOS）により構成する事が試みられて
いる。しかし相補型IGFETの特徴として、デコ
ーダ回路のような多入力回路では、構成に要する
IGFETの数が多く、この事により高速動作に適
さないという欠点がある。 However, recently, in order to save power, the word line drive circuit of nonvolatile semiconductor memory has been changed to a complementary type.
Attempts have been made to configure it using IGFET (CMOS). However, a characteristic of complementary IGFETs is that in multi-input circuits such as decoder circuits, the configuration requires
The disadvantage is that it has a large number of IGFETs, which makes it unsuitable for high-speed operation.
本発明の目的は、構成に要するIGFETの数が
少ない相補型信号線の駆動回路を提供することに
ある。 An object of the present invention is to provide a complementary signal line drive circuit whose configuration requires a small number of IGFETs.
本発明による信号線駆動回路は信号線と、該信
号線に第１の電位および基準電位の内の一方を印
加する手段と、該第１の電位よりも値の大きい第
２の電位が印加される電圧端子と、該電圧端子と
制御節点との間に接続された一チヤンネル（例え
ばＰチヤンネル）型の第１の電界効果トランジス
タと、該制御節点と上記基準電位の印加された基
準電位節点との間に接続された逆チヤンネル（例
えばＮチヤンネル）型の第２の電界効果トランジ
スタと、上記第１および第２のトランジスタのゲ
ートを上記信号線に接続する手段と、上記電圧端
子と上記信号線との間に接続され、ゲートが上記
制御節点に接続された一チヤンネル型の第３の電
界効果トランジスタとを有することを特徴とす
る。 A signal line driving circuit according to the present invention includes a signal line, a means for applying one of a first potential and a reference potential to the signal line, and a second potential having a value larger than the first potential. a first field effect transistor of one channel (for example, P channel) type connected between the voltage terminal and the control node; a reference potential node to which the reference potential is applied; a second field effect transistor of a reverse channel (for example, N-channel) type connected between the transistors, means for connecting the gates of the first and second transistors to the signal line, and the voltage terminal and the signal line. and a single-channel type third field effect transistor connected between the control node and the control node, and having a gate connected to the control node.
次に本発明を図面を用いて詳細に説明する。 Next, the present invention will be explained in detail using the drawings.
以下の実施例では信号線としてメモリのワード
線を駆動する場合について例示する。 In the following embodiment, a case where a word line of a memory is driven as a signal line will be exemplified.
第１図は本発明の実施例の３入力のデコーダ回
路を示す回路である。図において、Ｐ−ch型
IGFET Ｍ１，Ｍ２、及びＮ−ch型IGFET Ｍ
３，Ｍ４等から構成され、二つのアドレス入力信
号Ａ１，Ａ２が印加されている２入力NAND回
路の出力点１は、アドレス入力信号Ａ１及びＡ２
が論理１（読出し電源電圧Vccの＋5Vに相当）の
時だけ、論理０（接地電源に相当）になり、アド
レス入力信号Ａ１，Ａ２が他の論理状態では、出
力点１は全て論理１になる。この出力点１を入力
とし、Ｐ−ch型IGFET Ｍ５、Ｎ−ch型IGFET
Ｍ６の２つのIGFET等から構成される相補型論
理回路のうち一方のIGFET Ｍ６は、ソース接地
とし、他方のIGFET Ｍ５はソースをアドレス入
力信号Ａ３とし、双方のドレインをそれぞれ共通
接続し、これを相補型論理回路の出力とする。ま
た、この相補型論理回路の出力（出力点２）をド
レインとし、前記アドレス信号Ａ３とは逆論理な
アドレス信号３をゲート入力とし、ソースを接
地電源とするIGFET Ｍ７を設ける。このように
してＭ１〜Ｍ１１はデコーダ回路を構成する。次
に、前記相補型論理回路の出力点２とワード線
WLとの間にデプレーシヨン型IGFET Ｍ８を設
け、これを書込み信号によりゲート制御する。
更に、ワード線WLを入力とし、書込み時に高電
圧となる書込み用電源Vppと接地間に接続された
Ｐ−ch型IGFET Ｍ９、Ｎ−ch型IGFET Ｍ１０
を含む別の相補型反転論理回路を設ける。この回
路の出力（出力点３）を入力とし、ソースを書込
み用電源Vppとし、ドレインをワード線WLに接
続してなるＰ−ch型IGFET Ｍ１１を設けてい
る。尚、負荷容量C1はワード線WLに付加する容
量である。まず二つのアドレス入力信号Ａ１，Ａ
２のうちどちらかが論理０で出力点１の電位が論
理１の場合、IGFET Ｍ５がオフ、IGFET Ｍ６
がオン状態になり、アドレス入力信号A3の入力
状態にかかわらず、出力点２の電位は論理０にな
る。読出し状態では書込み信号は読出し用電
源電圧Vccの電位、書込み用電源電圧Vppは読出
し用電源電圧Vccと同電位に設定する。このた
め、デプレーシヨン型Ｍ８は読出し状態では常に
オンになり、ワード線WLの電位は出力点２と同
電位である接地電位になる。このワード線WLの
電位が論理１から論理０に放電に要する時間は、
IGFET Ｍ６，Ｍ８のコンダクタンスgmと負荷
容量C1により決定される。ワード線WLの電位が
論理０に決まると、IGFET Ｍ９がオン、
IGFET Ｍ１０がオフになり、出力点３の電位は
論理１になり、IGFET Ｍ１１はオフになり、書
込み用電源電圧Vppからワード線WLへの電流は
遮断される。IGFET Ｍ９〜Ｍ１１が本発明に係
わる駆動回路である。 FIG. 1 shows a three-input decoder circuit according to an embodiment of the present invention. In the figure, P-ch type
IGFET M1, M2, and N-ch type IGFET M
The output point 1 of the 2-input NAND circuit, which is composed of 3, M4, etc., and to which two address input signals A1 and A2 are applied, is the address input signal A1 and A2.
Only when is logic 1 (corresponding to +5V of read power supply voltage Vcc), becomes logic 0 (corresponds to ground power supply), and when address input signals A1 and A2 are in other logic states, output point 1 becomes logic 1. . Using this output point 1 as input, P-ch type IGFET M5, N-ch type IGFET
One of the complementary logic circuits consisting of two IGFETs, M6, etc., has a common source, and the source of the other IGFET M5 is the address input signal A3, and the drains of both are commonly connected. This is the output of the complementary logic circuit. Further, an IGFET M7 is provided, which has the output (output point 2) of this complementary logic circuit as its drain, the address signal 3 having the opposite logic to the address signal A3 as its gate input, and its source as the ground power supply. In this way, M1 to M11 constitute a decoder circuit. Next, output point 2 of the complementary logic circuit and the word line
A depletion type IGFET M8 is provided between the WL and the gate of the write signal.
Furthermore, the word line WL is input, and a P-ch type IGFET M9 and an N-ch type IGFET M10 are connected between the write power supply Vpp, which becomes high voltage during writing, and the ground.
Another complementary inverting logic circuit is provided. A P-ch type IGFET M11 is provided, which has the output (output point 3) of this circuit as its input, its source connected to the write power supply Vpp, and its drain connected to the word line WL. Note that the load capacitance C1 is a capacitance added to the word line WL. First, two address input signals A1, A
If either of 2 is logic 0 and the potential of output point 1 is logic 1, IGFET M5 is off, IGFET M6
is turned on, and the potential at output point 2 becomes logic 0 regardless of the input state of address input signal A3 . In the read state, the write signal is set to the potential of the read power supply voltage Vcc, and the write power supply voltage Vpp is set to the same potential as the read power supply voltage Vcc. Therefore, the depletion type M8 is always turned on in the read state, and the potential of the word line WL becomes the ground potential, which is the same potential as the output point 2. The time required for the potential of this word line WL to discharge from logic 1 to logic 0 is:
It is determined by the conductance gm of IGFETs M6 and M8 and the load capacitance C1 . When the potential of the word line WL is set to logic 0, IGFET M9 turns on.
IGFET M10 is turned off, the potential at output point 3 becomes logic 1, IGFET M11 is turned off, and current from write power supply voltage Vpp to word line WL is cut off. IGFETs M9 to M11 are drive circuits according to the present invention.
書込み状態では、IGFET Ｍ１１は書込み電圧
＋25Vが印加され、書込み信号が論理０にな
るが、IGFET Ｍ８がデプレーシヨン型のため、
出力点２の電位が論理０の場合、IGFET Ｍ８は
オン状態になり、ワールド線WLの電位は出力点
２と同様の接地電位となる。 In the write state, the write voltage +25V is applied to IGFET M11, and the write signal becomes logic 0, but since IGFET M8 is a depletion type,
When the potential at output point 2 is logic 0, IGFET M8 is turned on, and the potential at world line WL becomes the same ground potential as output point 2.
二つのアドレス入力信号A1，A2が共に論理１
の時だけ、出力点１の電位は論理０になり、
IGFET Ｍ５がオン、IGFET Ｍ６がオフにな
り、アドレス入力信号A3の入力状態により、ワ
ード線WLの電位は決定する。アドレス入力信号
A3が論理１の場合、IGFET Ｍ７はオフになり、
出力点２の電位はアドレス入力信号A3の電位と
同電位である論理１即ち電源Vccの電位になる。 Two address input signals A 1 and A 2 are both logic 1
Only when , the potential of output point 1 becomes logic 0,
IGFET M5 is turned on and IGFET M6 is turned off, and the potential of the word line WL is determined by the input state of the address input signal A3 . address input signal
If A 3 is logic 1, IGFET M7 is turned off,
The potential of the output point 2 becomes logic 1, which is the same potential as the potential of the address input signal A3 , that is, the potential of the power supply Vcc.
読出し状態では書込み信号が論理１である
ため、IGFET Ｍ８がオンして、ワード線WLは
出力点２と同電位である論理１になる。ワード線
WLの電位が論理１に決まる事により、IGFET
Ｍ９がオフ、IGFET Ｍ１１がオンになる。 Since the write signal is logic 1 in the read state, IGFET M8 is turned on and the word line WL becomes logic 1, which is the same potential as output point 2. word line
By determining the potential of WL to logic 1, IGFET
M9 turns off and IGFET M11 turns on.
ワード線WLの電位を論理０から１にするのに
要する時間は、IGFET Ｍ５，Ｍ８のコンダクタ
ンスgmと負荷容量C1とにより決定される。また、
書込み状態では書込み信号が論理０になるこ
とにより、IGFET Ｍ８のソースに＋5V、ゲー
トに0Vが印加されるため、オフになり書込み用
電源電圧Vppから読出し用電源電圧Vccへの電流
路は遮断され、ワード線WLは書込み用電源電圧
Vppの電位になる。なお、IGFET Ｍ８のしきい
値電圧VTは前記条件ソースに＋5V、ゲートに0V
印加した場合IGFET Ｍ８がオフする条件を満す
のに必要な値−5V以下である必要がある。 The time required to change the potential of the word line WL from logic 0 to 1 is determined by the conductance gm of IGFETs M5 and M8 and the load capacitance C1 . Also,
In the write state, when the write signal becomes logic 0, +5V is applied to the source of IGFET M8 and 0V is applied to the gate, so it is turned off and the current path from the write power supply voltage Vpp to the read power supply voltage Vcc is cut off. , word line WL is the write power supply voltage
The potential becomes Vpp. The threshold voltage V T of IGFET M8 is +5V for the source and 0V for the gate under the above conditions.
It needs to be less than -5V, which is the value necessary to satisfy the condition that IGFET M8 turns off when applied.
詳しく説明すると、IGFET Ｍ５がオンにな
り、出力点２の電位が電源電圧＋5Vになると、
ワード線WLの電位はIGFET Ｍ８を介して充電
され、IGFET Ｍ８がオフになる電位まで上昇す
る。この時のワード線WLの電位はIGFET Ｍ８
のしきい値電圧VTの絶対値になる。これにより
IGFET Ｍ１０がオンして出力点３の電位は下が
り、IGFET Ｍ１１がオンになり、ワード線WL
の電位は書込み用電源電圧Vppから充電され上昇
し、IGFET Ｍ８がオフである事より、IGFET
Ｍ１乃至Ｍ７により構成される読出し回路から遮
断され、最終的にはIGFET Ｍ９〜Ｍ１１の働き
によつて書込み用電源電圧Vppの電位（＋25V）
に駆動される。 To explain in detail, when IGFET M5 turns on and the potential of output point 2 becomes power supply voltage +5V,
The potential of word line WL is charged through IGFET M8 and rises to a potential where IGFET M8 is turned off. The potential of the word line WL at this time is IGFET M8
becomes the absolute value of the threshold voltage VT . This results in
IGFET M10 turns on, the potential at output point 3 decreases, IGFET M11 turns on, and the word line WL
The potential of IGFET increases as it is charged from the write power supply voltage Vpp, and since IGFET M8 is off, IGFET
The potential of the write power supply voltage Vpp (+25V) is cut off from the readout circuit constituted by M1 to M7, and finally by the action of IGFETs M9 to M11.
driven by
次に出力点１が論理０で、アドレス入力信号
A3が論理０の場合IGFET Ｍ７がオンして、出
力点２が論理０になるため、ワード線WLの電位
は論理０になる。 Next, output point 1 is logic 0, and address input signal
When A 3 is logic 0, IGFET M7 is turned on and the output point 2 becomes logic 0, so the potential of the word line WL becomes logic 0.
以上のように、書込み時はIGFET Ｍ８によ
り、書込み用電源電圧Vppから読出し用電源電圧
Vccへの電流路を遮断する事ができるため、読出
しに必要な回路と書込みに必要な回路とを容易に
分離することができる。この事により、高速読出
し動作が要求される回路を高い耐圧を必要としな
い最小チヤンネル長のIGFETにより構成する事
が可能になる。 As mentioned above, during writing, the IGFET M8 changes the power supply voltage for reading from the power supply voltage for writing Vpp to the power supply voltage for reading.
Since the current path to Vcc can be cut off, the circuit necessary for reading and the circuit necessary for writing can be easily separated. This makes it possible to configure a circuit that requires a high-speed read operation using an IGFET with a minimum channel length that does not require a high withstand voltage.
なお、本実施例の駆動回路では、定常的な消費
電力はほとんどないため、省電力化に適する。 Note that the drive circuit of this embodiment has almost no steady power consumption, and is therefore suitable for power saving.
このように、本発明によれば、ワード線を少な
い数のIGFETによつてVppに駆動できる。 As described above, according to the present invention, a word line can be driven to Vpp using a small number of IGFETs.
本発明は以上のような利点があり、特に大容量
メモリを設計するのに非常に大きな効果がある。 The present invention has the above-mentioned advantages, and is particularly effective in designing large-capacity memories.
第１図は本発明の実施例の駆動回路を示す回路
である。
尚図において、Ｍ１，Ｍ２，Ｍ５，Ｍ９，Ｍ１
１……Ｐ−ch型IGFET、Ｍ３，Ｍ４，Ｍ６，Ｍ
７，Ｍ１０……Ｎ−ch型IGFET、Ｍ８……ｎ−
chデプレーシヨン型IGFET、A1，A2，A3，3
……アドレス入力信号、……書込み信号、
WL……ワード線、Vcc……読出し用電源電圧、
Vpp……書込み用電源電圧、１，２，３……出力
点、C1……負荷容量。
FIG. 1 shows a driving circuit according to an embodiment of the present invention. In the figure, M1, M2, M5, M9, M1
1...P-ch type IGFET, M3, M4, M6, M
7, M10...N-ch type IGFET, M8...n-
ch depletion type IGFET, A 1 , A 2 , A 3 , 3
...Address input signal, ...Write signal,
WL...word line, Vcc...read power supply voltage,
Vpp...Writing power supply voltage, 1, 2, 3...Output point, C1 ...Load capacity.
Claims (1)
電位の内の一方を印加する手段と、該第１の電位
よりも値の大きい第２の電位が印加される電位端
子と、該電圧端子と制御節点との間に接続された
一チヤンネル型の第１の電界効果トランジスタ
と、該制御節点と前記基準電位の印加された基準
電位節点との間に接続された逆チヤンネル型の第
２の電界効果トランジスタと、前記第１および第
２のトランジスタのゲートを前記信号線に接続す
る手段と、前記電圧端子と前記信号線との間に接
続され、ゲートが前記制御節点に接続された一チ
ヤンネル型の第３の電界効果トランジスタとを有
することを特徴とする信号線駆動回路。1. A signal line, means for applying one of a first potential and a reference potential to the signal line, a potential terminal to which a second potential having a value greater than the first potential is applied, and the voltage a first field effect transistor of one channel type connected between a terminal and a control node; and a second field effect transistor of reverse channel type connected between the control node and a reference potential node to which the reference potential is applied. means for connecting the gates of the first and second transistors to the signal line; and a field effect transistor connected between the voltage terminal and the signal line, the gates of which are connected to the control node. A signal line drive circuit comprising a third channel type field effect transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62119737A JPS6323297A (en) | 1987-05-15 | 1987-05-15 | Signal line driving circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62119737A JPS6323297A (en) | 1987-05-15 | 1987-05-15 | Signal line driving circuit |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57161861A Division JPS5952497A (en) | 1982-09-17 | 1982-09-17 | Decoder circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6323297A JPS6323297A (en) | 1988-01-30 |
| JPH0330238B2 true JPH0330238B2 (en) | 1991-04-26 |
Family
ID=14768878
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62119737A Granted JPS6323297A (en) | 1987-05-15 | 1987-05-15 | Signal line driving circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6323297A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2636476B2 (en) * | 1990-07-17 | 1997-07-30 | 日本電気株式会社 | Nonvolatile semiconductor memory device |
| JP3080743B2 (en) * | 1991-12-27 | 2000-08-28 | 日本電気株式会社 | Nonvolatile semiconductor memory device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57143795A (en) * | 1981-03-03 | 1982-09-06 | Toshiba Corp | Nonvolatile semiconductor storage device |
-
1987
- 1987-05-15 JP JP62119737A patent/JPS6323297A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57143795A (en) * | 1981-03-03 | 1982-09-06 | Toshiba Corp | Nonvolatile semiconductor storage device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6323297A (en) | 1988-01-30 |
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