JPS62165369A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To facilitate manufacture of a semiconductor device such as an EP- ROM cell with simple processes and with a high reliability by a method wherein a part of 1st gate electrode material is selectively etched and isolated and the exposed surface of a substrate is doped with 2nd conductivity type impurity to form 2nd conductivity type diffused layers. CONSTITUTION:After resist is applied to 1st polycrystalline silicon film 34, a part of the 1st polycrystalline silicon film 34 is selectively etched and isolated with the resist as a mask. Then, after the resist is removed, the gate oxide film 33 which is exposed in a source forming region is removed by etching. Then a heat treatment is carried out and n<+> type diffused layers 35 are formed in the surfaces of a substrate 31 exposed in the source forming region. Successively, a PSG film formed on the 1st polycrystalline film 34 surface is removed. Then, diluted oxidation is carried out and a polycrystalline silicon oxide film 36 with the thickness of 300Angstrom is formed on the 1st polycrystalline silicon film 34 surface. At that time, hot oxide films 36' are formed on the n<+> type diffused layer 35 surfaces. 2nd polycrystalline silicon film 37 is deposited over the whole surface and then doped with phosphorus.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device.
, E2 PROM, and other non-volatile memories.

[Conventional technology]

FIG. 6 shows a plan view of an EFROM cell for 2 bits.

In FIG. 6, for example, a field oxide 111 is formed on the surface of a p-type silicon substrate, and a gate oxide film, a floating gate 2, an interlayer insulating film, and a control gate 3 are sequentially stacked on the substrate. Two rows of laminates are formed. The floating gate 2 is stacked on a gate oxide film formed on a substrate, and both ends thereof extend onto the field oxide film 1, and adjacent floating gates 2 are separated from each other on the field oxide film 1. There is. Further, the control gate 3 is formed in layers on an interlayer insulating film formed on the floating gate 2 and on the field oxide film 1, and extends over a large number of memory cell regions. Furthermore, 2
N+ type source and drain regions 4.5 are formed on the substrate surfaces on both sides of the column stack. The source region 4 is common to a number of memory cells, and the drain region 5 is surrounded by two columns of stacks and field oxide 111.

Conventionally, the above-mentioned EPROM cell has the structure shown in FIGS.
Manufactured by the method shown in d). In addition, Fig. 4(a)
, (b) is a cross section along the YY- line in FIG. 6, and FIG. 4 (C
) and (d) respectively show cross sections taken along the line zz' in FIG.

First, for example, a field oxide film 12 is formed on the surface of a p-type silicon substrate 11 by selective oxidation, and then a gate oxide film 13 is formed on the exposed surface of the substrate 11. Next, the first polycrystalline silicon containing impurities on its entire surface! After depositing 1114, using a resist (not shown) as a mask, the part shown by the broken line in FIG. 6 was etched by reactive ion etching (RIE).
selectively etched to separate them from each other. Subsequently, the resist is removed (as shown in FIG. 4(a)). Next, after forming a polycrystalline silicon oxide film 15 that will become a living room insulation film on the surface of the first polycrystalline silicon film 14, a second polycrystalline silicon film 16 containing impurities is deposited on the entire surface (see FIG.
b) As shown). Next, the second polycrystalline silicon film 16, the polycrystalline silicon oxide film 15, the first polycrystalline silicon film 14, and the gate oxide film 13 are sequentially etched by RIE using a resist (not shown) as a mask, and then etched on the substrate 11. Gate oxidation! 13. A stacked structure is formed in which a floating gate 17, a polycrystalline silicon oxide film 15, and a control gate 18 are sequentially stacked. Subsequently, the resist is removed (as shown in FIG. 3(C)). Next, for example, arsenic is ion-implanted using the control gate 18 as a mask, and then thermally treated in a dry oxygen atmosphere to form a thermal oxide film 19 on the exposed surfaces of the floating gate 17, control gate 18, and substrate 11. is activated to form n+ type source and drain regions 20.2) (as shown in FIG. 2(d)). Below, for example, CV
After depositing the D oxide film, a contact hole is opened on the drain region 2), and after the wiring metal is deposited on the entire surface,
Patterning is performed to form wiring, and an EPROM cell is manufactured.

[Problem that the invention seeks to solve]

By the way, in the conventional method, a source with a shallow junction,
A problem arises in that when a drain region is formed, normal cell operation cannot be obtained. This problem can be explained by x-X- in Figure 6.
The fifth section showing the cross section along the line (source line) in the order of the manufacturing process.
This will be explained with reference to Figures (a) to (C). That is, the fourth
The first polycrystalline silicon film 14 is formed in the step corresponding to FIG.
After separating and forming a polycrystalline silicon oxide film 15 in a step corresponding to FIG. 4(b), a second polycrystalline silicon film 16 is deposited on the entire surface. In the etched region, the polycrystalline silicon film 14 of No. 1 is deposited on the thermal oxide film 15' formed on the substrate 11 at the same time as the polycrystalline silicon oxide film 15 (FIG. 5(a)). (Illustrated). Next, in a step corresponding to FIG. 4(C), patterning is performed by RIE to form a TIG gate 70 and a control gate, and a thermal oxide film 15' and a second polycrystalline silicon film 16 are formed on the substrate 11. At the same time as the first polycrystalline silicon film 14, the substrate 11 is etched to form a groove 22 in the region where the first polycrystalline silicon film 14 had been deposited (as shown in FIG. 2B).

Next, in a step corresponding to FIG. 4(d), arsenic ions are implanted, and then heat treatment is performed in a dry oxygen atmosphere to form the source region 20. In this step, the source region 20 with a shallow junction depth is If this is attempted, arsenic ions are not implanted into the sidewalls of the grooves 22, so the source region 2) is divided by the sidewalls of the grooves 22 (as shown in FIG. It becomes impossible to obtain proper cell operation.

Further, after etching a part of the first polycrystalline silicon film 14 by RIE using a resist (not shown) as a mask in the step of FIG. 4(a), when removing the resist, RI
Metals associated with the E process may adhere to the side surfaces of the pattern of the first polycrystalline silicon film 14, or resist that cannot be removed may remain as carbon (C) on the top surface of the first polycrystalline silicon film 14. . When polycrystalline silicon oxide film 15 is formed on the surface of first polycrystalline silicon film 14 in the presence of such contaminants, polycrystalline silicon oxide film 1
Since a pinhole occurs in the floating gate, it becomes difficult to retain data in the floating gate.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a method for manufacturing highly reliable semiconductor devices such as EPROM cells using a simple process.

[Failure to solve the problem]

The method for manufacturing a semiconductor device of the present invention includes a step of forming a field insulating film on the main surface of a semiconductor substrate of a first conductivity type, a step of forming a gate insulating film on the exposed surface of the substrate, and a step of forming a first gate insulating film on the entire surface. After depositing the electrode material, there is a process of selectively etching and separating a part of it, a process of removing the exposed gate insulating film, and a process of doping the exposed substrate surface with impurities of the second conductivity type. a step of forming a second conductivity type diffusion layer; a step of forming an interlayer insulating film on the surface of the remaining first gate electrode material; a step of depositing a second goo 1 to electrode material on the entire surface; 2 gate electrode material, interlayer insulating film,
A step of sequentially patterning a first gate electrode material and a gate insulating film, and a step of forming source and drain regions by ion-implanting impurities of a second conductivity type using the pattern of the second gate electrode material as a mask. It is characterized by the following:

[Effect]

According to the above method, after selectively etching and separating a part of the first gate electrode material and removing the exposed gate insulating film, impurities of the second conductivity type are added to the exposed substrate surface. Since it is doped to form a second conductivity type diffusion layer, even if a groove is formed in the substrate when patterning the second gate electrode material, first gate electrode material, etc. in a later process, the groove will not be formed. A second conductivity type diffusion layer remains on the side surface. Therefore, even if source and drain regions with shallow junction depths are formed by ion implantation, the source regions will not be divided by the side surfaces of the trench, and the source resistance will not increase.

In addition, when forming the second conductivity type diffusion layer, for example, PoC
When heat treatment is performed in a λ atmosphere, a PSG film is formed on the exposed surface of the first gate electrode material, and contaminants on the surface of the first gate electrode material are taken in. therefore,
If an interlayer insulating film is formed after removing this PSG film,
An interlayer insulating film without pinholes can be formed, and data retention can be improved.

〔Example〕

Examples in which the method of the present invention is applied to the manufacture of EPROM cells are shown in FIGS. 1(a) to (d), FIGS. 2(a) to (d), and FIGS. 3(a) to (d). and explain. Note that FIGS. 1(a) to (d) are cross sections taken along the line X-X in FIG.
Figures 2 (a) to (d) are cross sections taken along line l-Y' in Figure 6, and Figures 3 (a) to (d) are cross sections taken along line z-z' in Figure 6. It is sectional drawing shown in order of a process.

First, a field oxide film 32 with a thickness of 0.8βl is formed on the surface of a p-type silicon substrate 31 with a specific resistance of 10 Ω-cm by selective oxidation, and then a film with a thickness of 20 μl is formed on the exposed surface of the substrate 31.
A gate oxide film 33 of 0 is formed. Next, after depositing a first polycrystalline silicon film 34 with a thickness of 0.4 mm over the entire surface,
Dope with phosphorus to give ρ5-20Ω/mouth. Continuing,
After a resist (not shown) is formed on the first polycrystalline silicon film 34, a portion of the first polycrystalline silicon film 34 is selectively etched and separated by RIE using this resist as a mask. Subsequently, after removing the resist, the gate oxide film 33 exposed in the source formation region is removed by etching. Subsequently, in POCn3 atmosphere, 900
A heat treatment is performed at .degree. C. for 10 minutes to form an n+ type resistive diffusion layer 35 having a junction depth of 0.3-1.rho.5-25 to 30 .OMEGA./hole on the surface of the substrate 31 exposed in the source formation region.

Next, the first polycrystalline silicon l! Remove the PSG film formed on the surface of 34 (Figure 1 (a), Figure 2 (
a) and FIG. 3(a) diagrammatically).

Next, diluted oxidation is performed at 1000° C. to form a polycrystalline silicon oxide film 36 with a thickness of 300 μm on the surface of the first polycrystalline silicon film 34. At this time, a thermal oxide film 36' is formed on the surface of the n1 type diffusion layer 35. Subsequently, after depositing a second polycrystalline silicon film 37 with a thickness of 0.4 mm over the entire surface,
Dope phosphorus. After this step, the n++ diffusion layer 35
phosphorus diffuses, and the junction depth becomes as deep as 0.5 tan (
(Illustrated in FIG. 1(b), FIG. 2(b), and FIG. 3(b)).

Next, after forming a resist (not shown) on the second polycrystalline silicon film 37, the second polycrystalline silicon film 37, the polycrystalline silicon oxide film 36, and the first polycrystalline silicon film are formed by RIE using this resist as a mask. 34 and gate oxide film 3
3 is sequentially etched to form a gate oxide film 33 on the substrate 31.
, floating gate 38 , polycrystalline silicon oxide film 3
6 and the control gate 39 are sequentially stacked to form a stacked body. At this time, in the source formation region, a part of the substrate 31 is etched simultaneously with the etching of the first polycrystalline silicon film 34 to form a groove 40. Some parts remain. Subsequently, the resist is removed (as shown in FIG. 1(C), FIG. 2(C), and FIG. 3(C)).

Next, using the control gate 39 as a mask, As+
Acceleration energy: 50 keV, dose: 5×1015
Ion implantation is performed under cIII4 conditions. Subsequently, by heat treatment at 950°C for 15 minutes in an oxygen atmosphere,
A thermal oxide film 41 is formed on the exposed surfaces of the floating gate 38, control gate 39, and substrate 31, and arsenic is activated to form a junction with a junction depth of 0.2mm and ρ5-40Ω/
Source and drain regions 42 and 43 are formed. Next, passivation 1144 with a film thickness of 0.5 cape on the entire surface
After depositing, a contact hole is formed on the drain region 43. Subsequently, after depositing an Aβ-81 film on the entire surface, patterning is performed to form a drain electrode 45, and EP
Manufacturing ROM cells (Fig. 1, (d), Fig. 2 (d)
and shown in FIG. 3(d)).

According to the method described above, a part of the first polycrystalline silicon film 34 is selectively etched in the step (a) of FIGS. 1 to 3, and the exposed gate oxide film 33 is etched. After that, an n+ type resistive diffusion layer 35 is formed on the surface of the substrate 31 exposed in the source formation region by heat treatment in a POCj2s atmosphere, and a 70-ting gate is formed in the process shown in FIGS. 1 to 3 (C). Even if a trench 40 is formed on the surface of the substrate 31 in the source formation region when patterning is performed to form the gate 38 and the control gate 39, a portion of the n+ type resistive diffusion layer 35 remains around the trench 40. For this reason, even if the source and drain regions 42 and 43 are formed with a shallow junction depth of 0.2 tan by ion implantation in the step (d) of FIGS. 1 to 3,
The source region 42 is not separated by the side surfaces of the groove 40. Therefore, it is possible to obtain an EPROM cell that does not have a high source resistance and exhibits normal cell operation.

Further, in the step (a) of FIGS. 1 to 3, heat treatment is performed in a POCng atmosphere to form an n+ type diffusion@35, and at this time, P formed on the surface of the first polycrystalline silicon film 34 is
Since the SG film is removed, contaminants remaining on the surface of the first polycrystalline silicon film 34 after the RIE process or resist removal process can be removed at the same time. Therefore, pinholes are not generated in the polycrystalline silicon oxide film 36 formed in the steps shown in FIGS. 1 to 3 (b).
, the data retention characteristics in the floating gate 38 can be improved.

In the above embodiments, the method of the present invention was applied to the manufacture of EPROM cells, but it goes without saying that the method of the present invention can be similarly applied to the manufacture of E2 PROM cells.

〔effect〕

As described in detail above, according to the method of the present invention, highly reliable semiconductor devices such as EPROM cells can be manufactured through extremely simple steps.

[Brief explanation of drawings]

FIGS. 1(a) to 1(d) show EPR in the embodiment of the present invention.
2(a) to 2(d) are cross-sectional views taken along line xx' in FIG. 6 showing a method for manufacturing an OM cell, and FIGS. 3(a) to 3(d) are sectional views taken along the line z-Y" in FIG.
Cross-sectional views along the z' line, Figures 4 (a) to (d) are the conventional E
Cross-sectional views showing the PROM cell manufacturing method, FIG. 5(a)-
(C) is a sectional view showing problems in the conventional manufacturing method, and FIG. 6 is a plan view of the EPROM cell. 31...p-type silicon substrate, 32...field oxide film, 33...gate oxide film, 34...first polycrystalline silicon film, 35...n+ type scattering layer 36.・・・
Polycrystalline silicon oxide film, 36'... thermal oxide film, 37.
... second polycrystalline silicon film, 38 ... floating gate, 39 ... control gate, 40 ...
Groove, 41... thermal oxide film, 42.43... n++ source, drain region, 44... passivation film, 4
5...Drain electrode.

Claims (3)

[Claims] (1) After forming a field insulating film on the main surface of a first conductivity type semiconductor substrate, forming a gate insulating film on the exposed substrate surface, and depositing a first gate electrode material on the entire surface, A process of selectively etching and separating a part of it, a process of removing the exposed gate insulating film, and a process of doping the exposed substrate surface with a second conductivity type impurity to form a second conductivity type diffusion layer. a step of forming an interlayer insulating film on the surface of the remaining first gate electrode material; a step of depositing a second gate electrode material on the entire surface; A step of sequentially patterning a first gate electrode material and a gate insulating film, and a step of forming source and drain regions by ion-implanting impurities of a second conductivity type using the pattern of a second gate electrode material as a mask. A method for manufacturing a semiconductor device, characterized in that: (2) After the step of doping the substrate surface exposed at the etched portion of the first gate electrode material with a second conductivity type impurity to form a second conductivity type diffusion layer, the first gate electrode material is removed. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising removing an insulating film formed on the surface of the semiconductor device. (3) Claim 1, characterized in that the pattern of the first gate electrode material is a floating gate, and the pattern of the second gate electrode material is a control gate.
A method for manufacturing a semiconductor device according to section 1.