JPS62165340A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS62165340A
JPS62165340A JP61006908A JP690886A JPS62165340A JP S62165340 A JPS62165340 A JP S62165340A JP 61006908 A JP61006908 A JP 61006908A JP 690886 A JP690886 A JP 690886A JP S62165340 A JPS62165340 A JP S62165340A
Authority
JP
Japan
Prior art keywords
fuses
fuse
semiconductor
redundant circuit
ion beam
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61006908A
Other languages
Japanese (ja)
Inventor
Haruki Komano
駒野 治樹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP61006908A priority Critical patent/JPS62165340A/en
Publication of JPS62165340A publication Critical patent/JPS62165340A/en
Pending legal-status Critical Current

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  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To cut fuses for a redundant circuit with a focusing ion beam without inflicting irradiation damage on semiconductor elements in the vicinities of the fuses and to contrive the improvement of element characteristics and the integration degree by a method wherein, with the focusing ion beam used for the cutting of the fuses, the installing places of the fuses are separated from the semiconductor elements as such as a prescribed distance. CONSTITUTION:In order to make a semiconductor memory provided with fuses for a redundant circuit, first a memory cell array 12 consisting of a plurality of semiconductor elements (such as MOS transistors) is formed on a semiconduc tor substrate 11. Moreover, an auxiliary circuit 13 consisting of a plurality of semiconductor elements and the redundant circuit consisting of a plurality of the fuses 14 are formed on the substrate 11 independent of the memory cell array 12. Here, the fuses 14 for the redundant circuit are formed at the positions separated about 15mum from the semiconductor elements of the auxiliary circuit 13. Then, a defective bit in the memory cell array 12 is detected and the fuse 14 for the redundant circuit, which corresponds to the defective bit, is cut with a focusing ion beam 15.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、冗長回路用のヒユーズを備えた半導体装置の
製造方法に係わり、特に冗長回路用のヒユーズを集束イ
オンビームで切断するようにした半導体装置の製造方法
に関する。
[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method of manufacturing a semiconductor device equipped with a fuse for a redundant circuit, and particularly relates to a method of manufacturing a semiconductor device having a fuse for a redundant circuit, and in particular a semiconductor device in which the fuse for the redundant circuit is cut by a focused ion beam. The present invention relates to a method for manufacturing a device.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

冗長回路用のヒユーズを備えた半導体装置、例えば半導
体メモリでは、不良のビットが発生した場合に冗長回路
用のヒユーズを切断して不良のビットを予備のビットに
置換えて、不良ビットによる欠陥を救済し、その製造歩
留りを上げている。
In semiconductor devices equipped with fuses for redundant circuits, such as semiconductor memories, when a defective bit occurs, the fuse for the redundant circuit is cut and the defective bit is replaced with a spare bit to relieve the defect caused by the defective bit. and increasing its manufacturing yield.

そして、冗長回路用のヒユーズを切断するには、従来、
レーザビーム等が用いられている。この場合、レーザビ
ームの径が数ミクロンと比較的大きいため、ヒユーズ間
をレーザビームの径部上に離す必要があり、これにより
集積度の低下を招いていた。
And, in order to cut the fuse for the redundant circuit, conventionally,
A laser beam or the like is used. In this case, since the laser beam has a relatively large diameter of several microns, it is necessary to space the fuses apart from each other on the diameter of the laser beam, which causes a reduction in the degree of integration.

そこで本発明者等は、冗長回路用のヒユーズの切断に、
集束イオンビームを用いることを考案した。この集束イ
オンビームは、サブミクロン程度に集束させることがで
き、且つこの程度に集束された状態であっても冗長回路
用のヒユーズを十分に切断することができる。従ってこ
の場合、冗長回路用のヒユーズ間距離を十分短くするこ
とができ、半導体装置の集積度の向上をはかることかで
き 1.I:  Q しかしながら、この種の方法にあっては次のような問題
を生じた。即ち、冗長回路用のヒユーズに照射した集束
イオンビームにより、ヒユーズ近傍にある半導体素子に
損傷を与え、その素子特性を悪化させることがある。集
束イオンビームによる半導体素子の照射損傷は、ヒユー
ズと半導体素子とを極端に離せば起こらないが、その場
合冗長回路用のヒユーズを備えた半導体装置はその分だ
け大きくなってしまい、集束イオンビームを用いる利点
が失われる。
Therefore, the inventors of the present invention solved the problem by cutting the fuse for the redundant circuit.
The idea was to use a focused ion beam. This focused ion beam can be focused to a submicron level, and even when it is focused to this level, the fuse for the redundant circuit can be sufficiently blown. Therefore, in this case, the distance between the fuses for the redundant circuit can be sufficiently shortened, and the degree of integration of the semiconductor device can be improved.1. I: Q However, this type of method has caused the following problems. That is, the focused ion beam irradiated to the fuse for the redundant circuit may damage the semiconductor element near the fuse and deteriorate the characteristics of the element. Irradiation damage to semiconductor devices by focused ion beams will not occur if the fuses and semiconductor devices are kept extremely far apart, but in that case, semiconductor devices equipped with fuses for redundant circuits will be correspondingly larger, making it difficult to use focused ion beams. The advantage of using it is lost.

(発明の目的〕 本発明は上記事情を角鑵してなされたもので、その目的
とするところは、冗長回路用のヒユーズ近傍の半導体素
子に照射損傷を与えることなく、集束イオンご−ムによ
り該ヒユーズを切断することができ、素子特性の向上及
び集積度の向上をはかり得る半導体装置の製造方法を提
供することにある。
(Object of the Invention) The present invention has been made by taking advantage of the above-mentioned circumstances, and its object is to use focused ion beams without damaging the semiconductor elements near the fuse for the redundant circuit. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can cut the fuse and improve device characteristics and integration.

本発明の骨子は、冗長回路用のヒユーズの切断に集束イ
オンビームを用いると共に、ヒユーズの設置箇所を半導
体素子から所定距離だけ離すことにある。
The gist of the present invention is to use a focused ion beam to cut fuses for redundant circuits, and to place the fuses at a predetermined distance from the semiconductor elements.

即ち本発明は、基板上に、複数の半導体素子を集積化し
てなる半導体集積回路と、複数の半導体素子からなる予
備回路及び複数のヒユーズからなる冗長回路とを予め形
成しておき、上記半導体集積回路中で不良が生じた半導
体素子に対応する上記冗長回路のヒユーズを切断し、該
素子を前記予備回路の素子と置換して不良素子の救済を
はかる半導体装置の製造方法において、前記ヒユーズを
前記半導体素子から15[μm]以上離してlll置し
、且つ該ヒユーズを切断する手段として集束イオンビー
ムを用いるようにした方法である。
That is, in the present invention, a semiconductor integrated circuit formed by integrating a plurality of semiconductor elements, a spare circuit consisting of a plurality of semiconductor elements, and a redundant circuit consisting of a plurality of fuses are formed in advance on a substrate, and the semiconductor integrated circuit is In the method for manufacturing a semiconductor device, the fuse of the redundant circuit corresponding to a semiconductor element that has failed in the circuit is cut off, and the redundant circuit is replaced with an element of the spare circuit to repair the defective element. In this method, the fuse is placed at a distance of 15 [μm] or more from the semiconductor element, and a focused ion beam is used as a means for cutting the fuse.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、冗長回路用のヒユーズを他の半導体素
子から15[μ711]以上離れた場所に設置している
ので、集束イオンビームによりヒユーズを切断した際に
も、ヒユーズ近傍の半導体素子に照射損傷が生じること
はない。従って、半導体素子の特性悪化を未然に防止す
ることができ、素子特性の向上をはかり得る。さらに、
集束イオンビームを用いているので、ヒユーズ間距離を
短くすることができ、集積度の向上にも有効である。
According to the present invention, since the redundant circuit fuse is installed at a distance of 15 μ711 or more from other semiconductor elements, even when the fuse is cut by a focused ion beam, the semiconductor elements near the fuse are No radiation damage occurs. Therefore, it is possible to prevent the characteristics of the semiconductor element from deteriorating, and it is possible to improve the characteristics of the element. moreover,
Since a focused ion beam is used, the distance between the fuses can be shortened, which is also effective in improving the degree of integration.

〔発明の実施例〕[Embodiments of the invention]

実施例を説明する前に、本発明の基本原理について説明
する。
Before explaining embodiments, the basic principle of the present invention will be explained.

集束イオンビームを半導体素子の近傍に照射した時の半
導体素子の照射損傷を調べるために、本発明者等は以下
の実験を行った。半導体素子としてはN−MOSトラン
ジスタを用い、集束イオンビームとしては加速電圧30
 [KV] 、ビーム径0.8[μm〕のGEi集束イ
オンビームを用いた。
In order to examine radiation damage to a semiconductor element when a focused ion beam is irradiated near the semiconductor element, the present inventors conducted the following experiment. An N-MOS transistor is used as the semiconductor element, and an accelerating voltage of 30 is used as the focused ion beam.
A GEi focused ion beam with [KV] and a beam diameter of 0.8 [μm] was used.

また、ビーム照射量は、冗長回路用のヒユーズを切断す
るのに必要な照射I(3×1018C#1′2)とした
Further, the beam irradiation amount was set to irradiation I (3×10 18 C#1'2) necessary for cutting the fuse for the redundant circuit.

まず、周知の工程により半導体基板上に、第3図に示す
如く、ゲート31及びソース・ドレイン32.33から
なるMOSトランジスタ30を複数個作成した。そして
、それぞれのトランジスタ30において、ゲート31か
ら異なる距離離した位置に前記集束イオンビーム35を
照射した。照射後の各トランジスタ30のドレイン電流
−ゲート電圧特性におけるゲート閾値電圧VTの変化を
第4図に示す。なお、第4図において、横軸は集束イオ
ンビーム35を照射した位置のゲート31からの距離×
[μm]、縦軸は閾値電圧の変化ΔVT [V]を示し
ている。この結果から、集束イオンビーム35をトラン
ジスタ30のゲート31から15Lμm]以上離して照
射すれば、トランジスタ30の特性は変化しないことが
判る。
First, as shown in FIG. 3, a plurality of MOS transistors 30 each consisting of a gate 31 and sources/drains 32 and 33 were formed on a semiconductor substrate by a well-known process. Then, in each transistor 30, the focused ion beam 35 was irradiated to positions separated by different distances from the gate 31. FIG. 4 shows changes in gate threshold voltage VT in drain current-gate voltage characteristics of each transistor 30 after irradiation. In addition, in FIG. 4, the horizontal axis is the distance from the gate 31 of the position irradiated with the focused ion beam 35 x
[μm], and the vertical axis indicates the change in threshold voltage ΔVT [V]. From this result, it can be seen that if the focused ion beam 35 is irradiated at a distance of 15 L μm or more from the gate 31 of the transistor 30, the characteristics of the transistor 30 will not change.

従って、冗長回路用のヒユーズを備えた半導体装置にお
いて、冗長回路用のヒユーズを半導体素子から15[μ
m]以上離した位置に設置すれば、集束イオンビームに
よりヒユーズを切断しても、ヒユーズ近傍にある半導体
素子へ損傷を与えるこ6一 とはない。
Therefore, in a semiconductor device equipped with a fuse for a redundant circuit, the fuse for the redundant circuit is separated from the semiconductor element by 15 [μ
If the fuses are installed at a distance of more than m], even if the fuse is cut by a focused ion beam, there will be no damage to semiconductor elements near the fuse.

以下、本発明の一実施例方法について第1図及び第2図
を参照して説明する。
Hereinafter, a method according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2.

冗長回路用のヒユーズを備えた半導体メモリを作成する
ために、まず第1図に示す如き構造を形成した。ここで
、第1図において11は半導体基板であり、この基板1
1上に複数の半導体素子(例えばMOS I−ランジス
タ)からなるメモリセルアレイ12を形成した。さらに
、メモリセルアレイ12とは別に、基板11上に複数の
半導体素子からなる予備回路13及び複数のヒユーズ1
4からなる冗長回路を形成した。ここで、冗長回路用の
ヒユーズ14は、予備回路13の半導体素子から約15
[μm]離した位置に形成した。
In order to create a semiconductor memory equipped with a fuse for a redundant circuit, a structure as shown in FIG. 1 was first formed. Here, in FIG. 1, 11 is a semiconductor substrate, and this substrate 1
A memory cell array 12 consisting of a plurality of semiconductor elements (for example, MOS I-transistors) was formed on the semiconductor device 1 . Furthermore, apart from the memory cell array 12, a preliminary circuit 13 consisting of a plurality of semiconductor elements and a plurality of fuses 1 are provided on the substrate 11.
A redundant circuit consisting of 4 was formed. Here, the fuse 14 for the redundant circuit is approximately 15 mm from the semiconductor element of the spare circuit 13.
They were formed at positions separated by [μm].

次いで、メモリセルアレイ12のうちで不良ビットを検
出し、該不良ビットに対応する冗長回路用のヒユーズ1
4を第2図に示す如く集束イオンビーム15により切断
した。このときの集束イオンビーム15の加速電圧、ビ
ーム径及び照射量等の条件は先に説明したのと同じにし
た。その結果、冗長回路用のヒユーズ近傍にある予備回
路13の半導体素子に照射損傷が生じることもなく、不
良ビットによる欠陥を救済することができた。
Next, a defective bit is detected in the memory cell array 12, and a redundant circuit fuse 1 corresponding to the defective bit is connected.
4 was cut by a focused ion beam 15 as shown in FIG. The conditions such as the acceleration voltage, beam diameter, and irradiation amount of the focused ion beam 15 at this time were the same as described above. As a result, the semiconductor element of the spare circuit 13 near the fuse for the redundant circuit was not damaged by radiation, and the defect caused by the defective bit could be repaired.

このように本実施例によれば、冗長回路用のヒユーズ1
4を予備回路13の半導体素子から15[μm]離した
位置に設置しておくことにより、半導体素子に照射損傷
を招くことなく、該ヒユーズ14を集束イオンビームに
より切断することができる。このため、メモリセルアレ
イ12の不良ビットの救済を行うことができるのは勿論
のこと、素子特性及び集積度の向上をはかり得る。
In this way, according to this embodiment, the fuse 1 for the redundant circuit
4 at a position 15 [μm] away from the semiconductor element of the preliminary circuit 13, the fuse 14 can be cut by the focused ion beam without causing radiation damage to the semiconductor element. Therefore, not only can defective bits in the memory cell array 12 be repaired, but also device characteristics and integration can be improved.

なお、本発明は上述した実施例方法に限定されるもので
はない。例えば、前記冗長回路用のヒユーズと半導体素
子との距離は15[μm]に限定されるものではなく、
それ以上であればよい。但し、集積度の点を考慮すると
、15[μm]に近い値が望ましい。また、半導体集積
回路としてはメモリセルアレイに限定されるものではな
く、複数の半導体素子を並列的に使用するものであれば
よい。さらに、集束イオンビームの加速電圧、ビーム径
及び照射量等の条件は、適宜変更可能である。その他、
本発明の要旨を逸脱しない範囲で、種々変形して実施す
ることができる。
Note that the present invention is not limited to the method of the embodiment described above. For example, the distance between the fuse for the redundant circuit and the semiconductor element is not limited to 15 [μm],
It is sufficient if it is more than that. However, considering the degree of integration, a value close to 15 [μm] is desirable. Further, the semiconductor integrated circuit is not limited to a memory cell array, but may be any circuit that uses a plurality of semiconductor elements in parallel. Furthermore, conditions such as the acceleration voltage, beam diameter, and irradiation amount of the focused ion beam can be changed as appropriate. others,
Various modifications can be made without departing from the spirit of the invention.

【図面の簡単な説明】[Brief explanation of drawings]

第1図及び第2図は本発明の一実施例方法に係わる半導
体メモリの製造方法を説明するためのもので第1図はヒ
ユーズ切断工程の前段階の装置構成を示す平面図、第2
図は集束イオンビームによるヒユーズ切断状態を示す模
式図、第3図及び第4図は本発明の基本原理を説明する
ためのもので第3図はMOSトランジスタの概略構成を
示す平面図、第4図は集束イオンビームの照射位置に対
する閾値電圧の変化を示す特性図である。 11・・・半導体基板、12・・・メモリセルアレイ(
半導体集積回路)、13・・・予備回路、冗長回路用ヒ
ユーズ、15・・・集束イオンビーム、30・・・MO
Sトランジスタ、31・・・ゲート、32・・・ソース
、33・・・ドレイン、35・・・集束イオンビーム。 出願人代理人 弁理士 鈴江武彦 =9− 第1図
1 and 2 are for explaining a method for manufacturing a semiconductor memory according to an embodiment of the present invention.
The figure is a schematic diagram showing a state in which a fuse is blown by a focused ion beam. Figures 3 and 4 are for explaining the basic principle of the present invention. Figure 3 is a plan view showing the schematic configuration of a MOS transistor. The figure is a characteristic diagram showing the change in threshold voltage with respect to the irradiation position of the focused ion beam. 11... Semiconductor substrate, 12... Memory cell array (
semiconductor integrated circuit), 13... reserve circuit, redundant circuit fuse, 15... focused ion beam, 30... MO
S transistor, 31...gate, 32...source, 33...drain, 35...focused ion beam. Applicant's agent Patent attorney Takehiko Suzue=9- Figure 1

Claims (2)

【特許請求の範囲】[Claims] (1)基板上に、複数の半導体素子を集積化してなる半
導体集積回路と、複数の半導体素子からなる予備回路及
び複数のヒューズからなる冗長回路とを予め形成してお
き、上記半導体集積回路中で不良が生じた半導体素子に
対応する上記冗長回路のヒューズを切断し、該素子を前
記予備回路の素子と置換して不良素子の救済をはかる半
導体装置の製造方法において、前記ヒューズを前記半導
体素子から15[μm]以上離して設置し、且つ該ヒュ
ーズを切断する手段として集束イオンビームを用いるこ
とを特徴とする半導体装置の製造方法。
(1) A semiconductor integrated circuit formed by integrating a plurality of semiconductor elements, a spare circuit formed from a plurality of semiconductor elements, and a redundant circuit formed from a plurality of fuses are formed in advance on a substrate, and in the semiconductor integrated circuit In the method of manufacturing a semiconductor device, the fuse of the redundant circuit corresponding to a semiconductor element that has become defective is cut off, and the redundant circuit is replaced with an element of the spare circuit to repair the defective element. A method for manufacturing a semiconductor device, characterized in that the fuse is placed at a distance of 15 [μm] or more from the fuse, and a focused ion beam is used as means for cutting the fuse.
(2)前記半導体集積回路は、メモリセルアレイである
ことを特徴とする特許請求の範囲第1項記載の半導体装
置の製造方法。
(2) The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor integrated circuit is a memory cell array.
JP61006908A 1986-01-16 1986-01-16 Manufacture of semiconductor device Pending JPS62165340A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61006908A JPS62165340A (en) 1986-01-16 1986-01-16 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61006908A JPS62165340A (en) 1986-01-16 1986-01-16 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS62165340A true JPS62165340A (en) 1987-07-21

Family

ID=11651334

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61006908A Pending JPS62165340A (en) 1986-01-16 1986-01-16 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS62165340A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0215654A (en) * 1988-04-25 1990-01-19 Zvi Orbach Customizable semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0215654A (en) * 1988-04-25 1990-01-19 Zvi Orbach Customizable semiconductor device

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