JP2916034B2 - Semiconductor integrated circuit and method of manufacturing semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and, more particularly, to a technique for improving the yield.
The present invention relates to a technology effective when applied to a static RAM (random access memory).

[0002]

2. Description of the Related Art A technique for improving the yield of a semiconductor integrated circuit by introducing redundancy into a chip can be used to relieve defects of memory cells which tend to increase with an increase in the degree of integration or storage capacity. .

Conventionally, a spare element for replacing a defective bit in a semiconductor memory device includes a spare row (spare row) including a redundant word line and a spare column (spare column) including a redundant bit line and the like in one of the memory cell arrays. Department.

When a defect is to be remedied for a semiconductor memory device having a redundant configuration such as a spare row or a spare column, a memory cell array in a chip is focused on through a wafer probe test or the like. , The position of the defective cell is detected. The position information of the defective cell obtained in this way is stored in a fail memory incorporated in a tester or an external device, and a redundancy program for replacing the defective bit with the defect repair bit according to the stored fail bit map is executed. Will be

When an address to be relieved is supplied to a semiconductor memory device to which a redundancy program has been applied, a redundancy address decoder for judging the address inhibits a normal address decoder from selecting a memory cell, and then sets a spare row or a spare. Addressing of the defect repair bits included in the column is performed by a spare decoder.

[0006] As an example of a document describing a redundant configuration, see "Nikkei Electronics" P189-P2 published by Nikkei McGraw-Hill on July 21, 1980.
01.

[0007] However, even if the repair is performed by selecting a memory cell having no defect as described above, if a current path from the load MOSFET to the ground line is formed in the defective memory cell, it cannot be repaired. Therefore, a DC leakage current flows, and particularly in a device having a battery backup function, a power supply current during standby increases, which is a serious problem.

As a technique for solving such a problem, for example, as described in JP-A-59-201298, a signal line of a normal memory cell group and this signal line are pulled up to a power supply line. There is known a technology in which an electrical conduction means capable of interrupting the supply of power is provided in a path to a transistor for performing the operation, and a leak current is reduced by interrupting this path when a defect is found. ing.

[0009]

The electrical conduction means is specifically a switch or a fuse provided for each bit line (data line). It has been found by the present inventor that the provision of may cause an increase in the number of chips due to an increase in the layout area.

In a wafer probe test of a semiconductor memory device or another semiconductor integrated circuit, a timing abnormality or the like may be found, and such a chip is generally removed as irreparable. The present inventor has clarified that this is a main factor that hinders the improvement in the yield of semiconductor integrated circuits.

An object of the present invention is to provide a technique capable of minimizing an increase in layout area for repairing defective bits.

An object of the present invention is to provide a technique capable of improving the yield of semiconductor integrated circuits.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0014]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, when a plurality of memory cells are coupled to each of a plurality of bit lines and a transistor for pulling up the bit line is coupled to form a semiconductor integrated circuit, a defective bit exists. By adjusting the threshold value of the transistor corresponding to the case, the current of the bit line coupled thereto is limited. A normal memory cell group in which a plurality of memory cells are coupled to each of the plurality of bit lines; and a normal selection means for selecting a corresponding memory cell from the normal memory cell group based on a given address signal. A spare memory cell group for relieving a defective bit included in the normal memory cell group, and a spare memory cell group for replacing a defective bit with a defect relief bit. A spare program circuit for performing a redundancy program; a spare selection means for selecting the spare memory cell group instead of the normal memory cell group based on the redundancy program of the spare program circuit; and the plurality of bit lines. And a transistor for pulling up a corresponding bit line. When it is, by adjusting the threshold value of the transistor corresponding thereto when a defective bit is present, to limit the current of the combined bit line thereto.

In a method of manufacturing a semiconductor integrated circuit in which a plurality of memory cells are coupled to each of a plurality of bit lines and a transistor for pulling up the bit lines, an operation test is performed on the wafer. Performing, and when it is determined in this operation test that a defective bit exists, registering the position of the transistor corresponding to the address of the column relief of the defective bit, and registering the corresponding transistor based on the registration information. Raising the threshold value of A normal memory cell group in which a plurality of memory cells are coupled to each of the plurality of bit lines; and a normal selection means for selecting a corresponding memory cell from the normal memory cell group based on a given address signal. A spare memory cell group for relieving a defective bit included in the normal memory cell group, and a spare memory cell group for replacing a defective bit with a defect relief bit. A spare program circuit for performing a redundancy program; a spare selection means for selecting the spare memory cell group instead of the normal memory cell group based on the redundancy program of the spare program circuit; and the plurality of bit lines. And a transistor coupled to each of the transistors for pulling up a corresponding bit line. In the method, a step of performing an operation test on the wafer, and if it is determined that a defective bit is present in the operation test, registering the position of the transistor corresponding to the address of the column relief of the defective bit, Raising the threshold value of the corresponding transistor based on the registration information.

[0017]

According to the above means, when it is determined that a defective bit exists in an operation test on a wafer, the threshold value of the corresponding transistor is raised, so that the driving capability of the transistor is reduced and the electric resistance is reduced. Is raised. The increase in the electrical resistance blocks the supply of power to the corresponding bit line, as if the conductive line were cut.
The above transistor is originally provided for pulling up a corresponding bit line. This achieves a reduction in DC leakage current without increasing the layout area.

[0018]

FIG. 3 shows a static RAM according to an embodiment of the present invention.

Although not particularly limited, the static RAM shown in FIG. 1 is formed on one semiconductor substrate by a known MOS integrated circuit manufacturing technique.

In FIG. 1, reference numeral 1 denotes a normal memory cell array in which a plurality of static memory cells are arranged in a matrix to form a normal memory cell group, and 2 denotes a selecting means for selecting words and columns of the normal memory cell array 1. A normal decoder 3 as an example is an address buffer for taking in an address signal. 4 is a spare memory cell column (or spare memory cell row) as a spare memory cell group, 5 is a spare decoder as spare memory selection means,
Reference numeral 6 denotes a spare program circuit for performing a redundancy program to replace a defective bit with a defect repair bit.

In the above configuration, when a defective portion is found in the normal memory cell array 1 by a test or the like, a fuse or switch provided in the output line of the normal decoder 2 or the spare program circuit 6 is turned on or off. Thereby, the spare memory cell column is selected instead of the memory cell column including the defective portion thereafter, and as a result, a memory cell having no defect can be selected for an arbitrary address.

FIG. 1 shows a detailed configuration of a main part of the static RAM.

As described above, according to the prior art, a path between a signal line of a normal memory cell group and a transistor for pulling up this signal line to a power supply line is connected to an electrically conductive means such as a switch or a fuse. The leakage current is reduced by blocking this path when a defect is found, but in the present embodiment, such a reduction in the leakage current can be achieved without increasing the layout area. To make this possible, the use of a conductive line shared by a plurality of bit lines eliminates the need to form the switches and fuses for each bit line.

As shown in FIG. 1, normal memory cell array 1 includes a plurality of memory cell columns 12-0 to 12-i, and each of memory cell columns 12-0 to 12-i has complementary bit lines BL0 and BL0. * (* Means signal inversion)-BL
A plurality of memory cells 10 are connected to each of i, BLi *. The memory cell 10 is of a static type. Reference numeral 7 denotes, although not particularly limited, a power supply line formed of an aluminum wiring layer, and conductive lines PDL0 to PDLi are coupled to the power supply line. These conductive lines PDL0 to PDLi are connected to complementary bit lines BL0, BL0 * to
Shared by BLi and BLi *. That is, the complementary bit lines BL0 and BL0 * are coupled to the conductive line PDL0 via the load MOSFET 9, and the complementary bit lines BL1 and BL0 *
L1 * is connected to the conductive line P via the load MOSFET 9.
DL1 and likewise complementary bit lines BLi, BL
i * is the conductive line PD via the load MOSFET 9
Bonded to Li. The above conductive lines PDL0 to PDLi
, The portions indicated by 8-0 to 8-i are normally connected, but are cut to reduce leakage current when a defective bit exists. This connection part 8-0 to 8
For -i, the wiring layer can be used as it is.
8-i may be formed by a fuse. Although not particularly limited, the load MOSFET 9 is an N-channel MOSFET. Reference numeral 11 denotes a column selection switch, which is turned on / off based on a decode output of the normal decoder 2 shown in FIG. The column selection switch 11 is coupled to a common data line (not shown). When the column selection switch 11 is selectively turned on, the bit line and the common data line are coupled to enable reading and writing of memory cell data. . The spare memory cell column 4 also includes a conductive line shared by the complementary bit lines, similarly to the normal memory cell array 1, and the power supply to the complementary bit line can be prevented by cutting the conductive line.

In the above configuration, the normal memory cell column 1
When a defective memory cell is included in 2-1, a spare memory cell column is selected as the memory cell column 12-1 in place of the spare memory cell column 4 shown in FIG. Memory cells can be selected without failure. At this time, the connection portion 8-1 is disconnected, and the power supply from the power supply line 7 to the complementary bit lines BL1 and BL1 * is blocked. Such a connection can be cut by applying a resist to the entire surface of the wafer and etching only the connection to be cut, or by irradiating an electron beam, an ion beam, or a laser. In the case of cutting with a beam or a laser, it is not always necessary to apply a resist to the entire surface of the wafer as long as the beam diameter is smaller than the cut portion and if partial irradiation is possible.

Even if a current path from the load MOSFET 9 to the ground line is formed in the defective memory cell column 12-1 by cutting the connection as described above, it is possible to prevent a DC leakage current caused by the current path. . Since the conductive line PDL1 is shared by the complementary bit lines BL1 and BL1 *, the power supply to the complementary bit lines BL1 and BL1 * can be prevented by cutting only the connection portion 8-1. In other words, by using a conductive line shared by a plurality of bit lines, it is not necessary to form the switches and fuses for each bit line, and it is possible to reduce the leak current without increasing the layout area. .

FIG. 2 shows another embodiment.

In the static RAM shown in FIG. 1, a conductive line is shared for each complementary bit line. However, as shown in FIG. 2, a single conductive line is shared by more bit lines. It can be configured as follows. That is, in the configuration shown in FIG. 2, complementary bit lines BL0, BL0 * to BLn, BLn * are coupled to conductive line PDL0 via load MOSFET 9, and connection portion 80-0 on conductive line PDL0 is disconnected. The complementary bit lines BL0, BL0 *
To BLn and BLn *. This is particularly effective when the number of data that can be set by one address designation is n, that is, when the memory has a × n-bit configuration. As described above, as the number of bit lines sharing a single conductive line is larger, the layout area is further reduced as compared with the case where a switch or the like is provided for each bit line.

A method for manufacturing the above static RAM will be described.

FIG. 5 shows the flow of a method according to an embodiment of the present invention.

The connection portions 8-0 to 8-i in FIG. 1 and the connection portion 80-0 in FIG. 2 are formed on the final wiring layer or the uppermost wiring layer on which a wafer probe test can be performed (step 51). ). At the stage when this final wiring layer or the top wiring layer is formed, a wafer probe test is performed,
A defective bit is detected (step 52), and the presence / absence of a defective bit is determined (step 53). If it is determined that there is a defective bit in this determination, the position of the connection portion corresponding to the address of the column repair of the defective bit is detected, and this is detected by the laser device or FIB (Foc).
It is registered in a device capable of etching at a specific position such as a used ion beam device (step 54), and the registered position is etched (step 55). By such an etching process, power supply to a memory cell column including a defective bit is prevented. Then, after such etching, a protective film is applied to the chip (step 56). If it is determined in step 53 that there is no defective bit, the above-described protective film is formed without performing the above-described etching process.

As described above, the connection portions 8-0 to 8-i and the connection portion 80-0 in FIG. 2 are formed on the final wiring layer or the uppermost wiring layer on which the wafer probe test can be performed. In addition, when the defective bit exists, the above etching process can be easily performed.

FIG. 6 shows the flow of a method according to another embodiment of the present invention.

Similarly to the method of the above embodiment, the connection portions 8-0 to 8-i in FIG. 1 and the connection portion 80-0 in FIG.
It is formed on the final wiring layer or the uppermost wiring layer that enables the wafer probe test (step 61). At the stage where the final wiring layer or the uppermost wiring layer is formed, a wafer probe test is performed, a defective bit is detected (step 62), and a determination is made as to whether or not a defective bit exists (step 63). If it is determined that there is a defective bit in this determination, the position of the connection portion corresponding to the column relief address of the defective bit is detected and registered in the laser device or FIB device (step 64). At this time, when there is a spare memory cell for column rescue that is unnecessary in circuit in such rescue, that is, when spare memory cells not used for rescue of defective bits are included in spare memory cell column 4 The position of a conductive line for supplying power to the spare memory cell or a connection portion thereof is also determined by the laser device or the FIB.
It is registered in the device (step 64). After the registration, the registered position is etched by a device capable of etching a specific position such as a laser device or an FIB device (step 65). By such an etching process, power supply to the memory cell column including the defective bit and the unnecessary memory cell column in the spare memory cell column 4 is prevented. Then, after such etching, a protective film is applied to the chip (step 66).
If it is determined in step 63 that there is no defective bit, the above-described protective film is formed without performing the above-described etching process.

As described above, when a spare memory cell which is not used for repairing a defective bit is included in spare memory cell column 4, a conductive line for supplying power to the spare memory cell or a connection position of the conductive line is provided. Is registered in the laser device or the FIB device, and an etching process is performed based thereon, thereby preventing power supply to a spare memory cell not used for repairing a defective bit, thereby suppressing unnecessary current consumption. This is effective in reducing current consumption.

The above-described bit rescue can be realized by cutting the program for the spare program circuit 6, specifically, by cutting a fuse or the like (only a wiring layer) provided in the spare program circuit 6. However, such a program can be performed as shown in FIG.

That is, when the final wiring layer or the uppermost wiring layer is formed, a wafer probe test is performed,
A defective bit is detected (step 72), and the presence or absence of a defective bit is determined (step 73). If it is determined in this determination that a defective bit exists, the cutting position of the final wiring layer in the spare program circuit 6 is registered in the laser device or the FIB device in order to remedy it (step 74). After the registration, the registered position is etched by the laser device or the FIB device (step 75). By such an etching process, a program for relieving a defective bit is completed, and after such etching, a protective film is applied to the chip (step 76). If it is determined in step 73 that there is no defective bit, the above-described protective film is formed without performing the above-described etching process. Here, when the registration for the program (step 74) is performed, the connection position registration in step 54 in FIG. 5 and step 64 in FIG. 6 is performed, so that the etching based on such registration is also performed. It can be carried out.

FIG. 8 shows another embodiment method.

First, as in the case of the above-described reference example, a final wiring layer or a top wiring layer capable of performing a wafer probe test is formed (step 81). At the stage when the final wiring layer or the uppermost wiring layer is formed, a wafer probe test is performed, a defective bit is detected (step 82), and a determination is made as to whether a defective bit exists (step 83). If it is determined that there is a defective bit in this determination, the position of the load MOSFET corresponding to the address of the column repair of the defective bit is detected and registered in the high energy implanter (step 84).
After the registration is made, the threshold value of the registered load MOSFET is raised by the high energy implantation device. Such a rise in the threshold value lowers the driving capability of the MOSFET and increases the electric resistance, so that power supply to a predetermined bit line is blocked in the same manner as when the conductive line is cut in the above-described embodiment. . After such a rise in the threshold value, a protective film is applied to the chip (step 86). If it is determined in step 83 that there is no defective bit, the above-described protection film is formed without increasing the threshold value.

According to the above embodiment, the following effects can be obtained.

(1) Conductive lines PDL0 to PDLi for supplying power to a plurality of bit lines are shared by the plurality of bit lines, and by cutting the conductive lines, power is supplied to the corresponding bit lines. Therefore, there is no need to provide a switch or the like for reducing the DC leakage current, and an increase in the layout area for repairing the defective bit can be suppressed as much as possible. That is, the conductive lines PDL0 to PDLi shared by a plurality of bit lines
Utilizing the method makes it unnecessary to form a switch and a fuse for each bit line, and can reduce the leak current without increasing the layout area.

(2) When a spare memory cell not used for repairing a defective bit is included in spare memory cell column 4, a conductive line for supplying power to the spare memory cell or a position of a connection portion thereof is set. Since the power supply to the spare memory cells not used for repairing the defective bit is prevented by performing the etching based on the registration in the laser device or the FIB device, unnecessary current consumption can be suppressed. Thus, current consumption can be reduced.

(3) By forming the conductive lines PDL0 to PDLi each including the connection portions 8-0 to 8-i with the uppermost wiring layer or a wiring layer capable of performing a wafer probe test, after the wafer probe test, Can be easily disconnected.

(4) With the high energy implantation device,
Since the threshold value of the load MOSFET is increased, and the drive capability of the MOSFET is reduced and the electric resistance is increased by such an increase in the threshold value, a predetermined value is obtained in the same manner as when the conductive line is cut by the method of the above embodiment. Power supply to the bit line is blocked. Therefore, it is not necessary to form a switch or a fuse for each bit line as in the case of cutting the conductive line by the method of the above embodiment, and it is possible to reduce the DC leakage current without increasing the layout area.

Although the invention made by the inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof. No.

In the above embodiment, the power supply to the bit line is blocked by cutting off the connection portion 8-1 and the like.
Although a description has been given of a case where the same effect is obtained by increasing the threshold value of ET9, the present invention is not limited to this. For example, when a defect is detected in a wafer probe test or the like, the defect may be registered in a large computer or the like, and the defect may be eliminated by changing the wiring based on the registered information. FIG. 4 shows the steps in that case.

That is, at the stage when the final wiring layer or the uppermost wiring layer is formed, a wafer probe test is performed (step 41), and a defect is detected (step 4).
2), the presence or absence of a defect is determined (step 43).
If it is determined in this determination that a defect exists, the content of the defect is input to the computer. In the electronic computer, corresponding information is selected from information stored in advance as a means for solving the input defect information, and the selected information is set in a laser device, an FIB device, or the like (step 44). With such an information set, the wiring is changed on the wafer by a laser device, a FIB device, or the like (step 45), whereby the above-mentioned problem is solved, and then a protective film is formed. If it is determined in step 43 that there is no problem, the above-described protection film is formed without changing the wiring. Here, the above-mentioned problems include timing abnormalities and insufficient drivability.For example, in the case of timing abnormalities, a wiring change for changing the number of stages of elements forming a delay circuit can be changed in a final wiring layer or the like. Such a problem can be easily solved by forming the drive element and replacing the drive element or connecting a plurality of elements in parallel for insufficient drivability. The wiring can be changed by etching or deposition.

As described above, the step of performing an operation test on a wafer formed so as to be capable of changing a circuit, and, when a defect is detected in the operation test, setting as a circuit change content for eliminating the defect in advance. And a step of performing an etching process or a deposition process on the wafer based on the obtained information, thereby easily resolving the problem and improving the yield of the semiconductor integrated circuit.

In the above description, the invention made by the present inventor has been mainly described with respect to the static RAM, which is a field of application that is the background of the invention. However, the present invention is not limited to this, and other semiconductors such as a dynamic RAM The present invention can be widely applied to storage devices, and other semiconductor integrated circuits formed by semiconductor integrated technology.

The present invention can be applied on condition that at least a wiring layer is included.

[0051]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, when a defective bit exists,
The threshold value of the corresponding transistor for pulling up the bit line is increased, and such a rise in the threshold value lowers the driving capability of the transistor and increases the electrical resistance of the transistor. Power supply is blocked. For this reason, it is not necessary to form a switch or a fuse for blocking the power supply to the bit line for each bit line, so that the DC leakage current can be reduced without increasing the layout area.

[Brief description of the drawings]

FIG. 1 shows a static R according to an embodiment of the present invention.
FIG. 3 is an electrical connection diagram showing a configuration of a main part in AM.

FIG. 2 is an electrical connection diagram showing a configuration of a main part in a static RAM according to another embodiment of the present invention.

FIG. 3 is a block diagram showing an overall configuration of a static RAM;

FIG. 4 is a flowchart illustrating an embodiment of a method of manufacturing a semiconductor integrated circuit.

FIG. 5 is a flowchart showing another embodiment of the method of manufacturing a semiconductor integrated circuit.

FIG. 6 is a flowchart illustrating another embodiment of a method of manufacturing a semiconductor integrated circuit.

FIG. 7 is a flowchart showing another embodiment of the method of manufacturing a semiconductor integrated circuit.

FIG. 8 is a flowchart showing another embodiment of the method of manufacturing a semiconductor integrated circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Normal memory cell array 2 Normal decoder 3 Address buffer 4 Spare memory cell column 5 Spare decoder 6 Spare program circuit 7 Power supply line 8-0 to 8-i Connection part 9 Load MOSFET 10 Memory cell 11 Column selection switch 12-0 to 12- i Memory cell column PDL0 to PDLi Conductive line BL0, BL0 * to BLi, BLi * Bit line

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G11C 29/00 H01L 21/66 H01L 21/82

Claims (4)

(57) [Claims] In a semiconductor integrated circuit in which a plurality of memory cells are coupled to each of a plurality of bit lines and a transistor for pulling up the bit line is coupled, when a defective bit exists, A semiconductor integrated circuit wherein a current of a bit line coupled thereto is limited by adjusting a threshold value of a corresponding transistor. 2. A normal memory cell group comprising a plurality of memory cells coupled to each of a plurality of bit lines, and a memory cell group for selecting a corresponding memory cell from the normal memory cell group based on a given address signal. A normal selection unit; a plurality of memory cells coupled to each of the plurality of bit lines; a spare memory cell group for relieving a defective bit included in the normal memory cell group; A spare program circuit for performing a redundancy program for replacement; and
Preliminary selection means for selecting the spare memory cell group instead of the normal memory cell group, and a transistor coupled to each of the plurality of bit lines and pulling up a corresponding bit line 2. A semiconductor integrated circuit according to claim 1, wherein when a defective bit is present, a threshold value of said transistor corresponding to said defective bit is adjusted to limit a current of a bit line coupled to said transistor. 3. A method for manufacturing a semiconductor integrated circuit comprising: a plurality of memory cells coupled to each of a plurality of bit lines; and a transistor for pulling up the bit line, wherein the operation is performed on a wafer. Performing a test; and, if it is determined in the operation test that a defective bit is present, registering the position of the transistor corresponding to the column relief address of the defective bit. Increasing the threshold value of the transistor. A method for manufacturing a semiconductor integrated circuit, comprising: 4. A normal memory cell group in which a plurality of memory cells are coupled to each of a plurality of bit lines, and a memory cell group for selecting a corresponding memory cell from the normal memory cell group based on a given address signal. A normal selection unit; a plurality of memory cells coupled to each of the plurality of bit lines; a spare memory cell group for relieving a defective bit included in the normal memory cell group; A spare program circuit for performing a redundancy program for replacement; and
Preliminary selection means for selecting the spare memory cell group instead of the normal memory cell group, and a transistor coupled to each of the plurality of bit lines and pulling up a corresponding bit line In the method of manufacturing an integrated circuit, a step of performing an operation test on the wafer; and, when it is determined in the operation test that a defective bit exists, registering the position of the transistor corresponding to the address of the column repair of the defective bit. And a step of increasing the threshold value of the corresponding transistor based on the registration information.