JPS62164321A - Sequential decoder - Google Patents

Abstract

PURPOSE:To minimize a circuit scale and to execute the highly speedy processing by normalizing a pass metric and a threshold. CONSTITUTION:The decoder is provided with the first adder 1 to add the previous pass metric from a pass metric register 7 and a threshold DELTA, a subtractor 2 to subtract a backward branch metric from the pass metric, the second adder 3 to add the pass metric and a forward branch metric, a calculating part 4 to modulo-calculate the output of the second adder 3 at the increase and decrease width DELTA of the threshold, a selector 5, and a pass deciding part 6 to control the selector 5 by the output of the subtracter 2 or the second adder 3. By the selector 5, the pass metric from the pass metric register 7, the output of the first and second adders 1 and 3, the output the subtracter 2 and the output of the calculating part 4 are selected, and added to a pass metric register 6 as the present pass metric.

Description

[Detailed Description of the Invention] [Summary] In a sequential decoder that decodes convolutional codes using the Fano algorithm, the path metric and threshold are normalized to reduce the circuit scale of the sequential decoder.

[Industrial application field]

The present invention uses convolutional codes (convolutional codes).
By normalizing the path metric and threshold value, the Fano algorithm is applied.
hm).

As a decoding method for decoding convolutional codes, the threshold decoding method (
threshold decoding), maximum likelihood decoding (ma-ximum 1ikelihood decoding)
oding) and sequential decoding method (sequential decoding method)
(sequential decoding). The fan algorithm is the main decoding algorithm of the sequential decoding method, and calculates the path value between one path in the dendritic code and the received sequence, and if the path value is less than the threshold, This algorithm decodes the information bits, and if the path value exceeds the value, it is assumed that the path has entered an error path, searches for the correct path, and decodes the correct information bits.

[Conventional technology]

The sequential decoder is composed of a path memory, an internal encoder, an adder for path metrics and branch metrics, and means for comparing and determining the addition result with a threshold value, and decodes the convolutional code using the Fano algorithm.

Figure 3 is an explanatory diagram of the Fano algorithm, in which the previous path metric and the current branch metric are added together to obtain the current path metric, which is compared with a threshold. and the threshold. (2), (path metric of 31 points and threshold 2D
(4) The path metric of the point and the threshold 3Do
The path metrics of points (51, (6), (7)) are compared with the threshold 4Do.

(At points 11 to (7), if the path metric does not fall below the threshold value, that is, if the path metric increases sequentially and does not reach a value below the threshold value, a forward bus search is performed and the previous path is determined to be correct and is stored in the path memory as the path history.

At the next point (8), the path metric becomes less than the threshold 4Do at the previous point (7), and becomes a small value that cuts this threshold 4Do, so a path search by backwards is performed, and the path metric becomes less than the threshold 4Do at the previous point (7). Using the path history of the code constraint division that includes the path history of the previous point (7) stored in memory, other paths that do not cut the threshold 4D, that is, the threshold 4Do
It is determined whether there is another path with a path metric of the above value. If it is determined that no other path exists,
The path to point (7) is determined to be an error, and another path that does not exceed the threshold 4Do exists by using the path history of the code constraint division that includes the path history of the previous point (6). Determine whether or not. At this time, if point 09 is another path that does not cross the threshold 4D, it is considered the correct path, and the process moves from searching for a backward path to searching for a forward path, and at the next (b) point. Determination processing is performed.

Also, if there is no other path that does not cut the threshold 4D, such as point 00, or if there is no measurement point and the α1 point next to point 09 has a small value that cuts the threshold 4Do, then the previous (5
) It is determined whether there is a path that does not exceed the threshold value 4D, using the path history of the code constraint division including the path history of the point. Then, if the 00 points also have a small value below the threshold 4D, (5) all paths of points will have small values below the threshold 4D, and then search for paths by lowering the threshold to 3D. . As a result, the α-minute point does not cross the threshold 3D, but the next α9 point has a small value that crosses the threshold 3Do, so it is determined that the path passing through point Q4) is not the correct path.

Therefore, the path from point (7) to point (8) has a value that does not fall below the threshold 3D, so it is judged as a correct path this time, but at the next point (9), a value smaller than the threshold 3D is determined. Therefore, it is determined that the path is an error. Therefore, the aforementioned backward bus search is performed, and if there is no path that does not exceed the threshold 3D, the threshold is further lowered to 2D. With this threshold value 2D, the path up to point (9) is also determined to be correct, and the forward search for the path is continued.

Since it is a large value that does not exceed , it is determined that the path is correct.

[Problem that the invention seeks to solve]

The current branch metric and the previous path metric are added to become the current path metric, and if the path metric increases sequentially, the thresholds are also Do, 2D, 3D.

, . . . , and the number of bits to be operated on is also large (this has the disadvantage of increasing the circuit scale).

An object of the present invention is to reduce the circuit scale.

[Means for solving problems]

The sequential decoder of the present invention normalizes path metrics each time a maximum likelihood path is selected, and will be described with reference to FIG. A first adder 1 that adds the previous path metric from the path metric register and a threshold value Δ
a subtracter 2 that subtracts a backward branch metric from the path metric; a second adder 3 that adds the path metric and the forward branch metric;
an arithmetic unit (mod Δ) 4 that performs a modulo operation on the output of the adder 3 by the increase/decrease width Δ of the threshold value, a selector 5, and a subtracter 2;
or a path determination unit 6 that controls the selector 5 based on the output of the second adder 3; , the output of the subtracter 2, and the output of the arithmetic unit 4 are selected and added to the path metric register 6 as the current path metric.

[Effect]

The output of the first adder 1 is the path metric plus the threshold Δ, which is equivalent to lowering the threshold. Also, the output of the subtractor 2 is the path metric of the backward path obtained by subtracting the backward branch metric during the backward path search from the previous path metric, and the output of the adder 3 of the writer 2 is the previous path metric and the forward path metric. The path metric of the forward path is obtained by adding the forward branch metric during the search. Further, since the output of the calculation unit 4 is obtained by performing a modulo calculation with the increase/decrease width Δ of the threshold value, the path metric of the forward path is normalized.

If the output of the subtracter 2 and the output of the second adder 3 are within the threshold, the sign bit will not change, but if the threshold is exceeded, the addition result will overflow or the subtraction will occur. The result is an underflow condition,
Since the sign bit is inverted, by identifying the sign bit of the path metric of the backward path or the sign bit of the path metric of the forward path, it is possible to easily determine whether or not the threshold value has been reached.

The path determination unit 6 determines the above-mentioned sign bit and controls the selector 5, and during forward path searching, if the sign bit of the path metric of the forward path is not inverted, the threshold value is not crossed. Because there is, this passme I
- If the link is selectively output and the sign bit is inverted and the threshold value is exceeded, the path metric normalized by the calculation unit 4 is selectively output.

Also, when searching for a path by backwards, if the sign bit of the path metric of the backward path is not inverted, the threshold will not be crossed, so if that path metric is selectively output and the sign bit is inverted and the threshold is crossed. selects and outputs a path metric with a lowered threshold of the output of the first adder 1.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a functional block diagram of an embodiment of the present invention, in which the previous path metric from the bus metric link register 7 is added to the selector 5, and the path metric and
The threshold value Δ is added by the first adder l, and the path metric with the lowered threshold value is output and added to the selector 5. Further, the backward branch metric link at the time of path search by backtracking is subtracted from the previous path metric from the path metric register 7 by the subtracter 2, and the path metric of the backward bus is output and added to the selector 5. Further, the previous path metric from the path metric register 7 and the forward branch metric at the time of forward path search are added by the second adder 3, and the path metric of the forward path is output and added to the selector 5.

Further, the arithmetic unit 4 performs a modulo operation on the output of the second adder 3 by the increase/decrease width Δ of the threshold value, and the normalized path metric of the forward path is output and added to the selector 5 . for example,
The increase/decrease width Δ of the threshold value is expressed as a 4-bit decimal number “1”.
6'', the modulo operation of the increase/decrease width Δ corresponds to outputting only the lower 4 bits of the output of the second adder 3. This can be achieved with functions.

The subtracter 2 and the second adder 3 perform subtraction or addition of a predetermined number of bits, and the most significant bit is the sign bit. If it goes low, the sign bit will be inverted. Therefore, by adding the sign bits of the subtraction result and addition result to the path determination unit 6, it is possible to determine whether the subtraction result is below the threshold value or whether the addition result is below the threshold value. can be determined. Selector 5 depending on the result
is used to selectively output path metrics.

For example, during a forward path search, if the sign bit of the path metric of the forward path obtained by adding the previous path metric and the forward branch metric by the second adder 3 is not inverted, it means that the threshold is not crossed. The path determination unit 6 controls the selector 5 to selectively output this path metric. When the path determination section 6 determines that the sign bit has been inverted, the selector 5 is controlled to selectively output the normalized path metric output from the calculation section 4.

Also, when searching for a path by backwards, if the sign bit of the path metric of the backward path output from subtractor 2 is not inverted,
Selector 5 so that the path metric is selectively output.
is controlled by the path determination section 6. When the path determining section 6 determines that the sign bit has been inverted, the selector 5 is controlled by the path determining section 6 so that the output of the first adder 1 is selectively output.

If the path metric of the path depth is n is Ln, and the branch metric is λn, then the threshold is T, and the increase/decrease range of the threshold T is Δ, then T=m・Δ − (2) However,
m is an integer.

The relationship between the path metric and the threshold when a path is selected for the first time is T≦Ln<T+Δ − (3).

Expressing the path metric as a value relative to the threshold value, L n ' = L n -T ゛ (4), and from equation (3), 0≦l, n -'l'<Δ 0≦L n 1 <Δ, that is, , the path metric nt expressed as a relative value falls within the range of increase/decrease Δ of the threshold T. Then, when you select a path for the first time, normalize it as follows.

Ln’=Ln”mod　Δ Also, when lowering the threshold, Ln’←Ln’+Δ becomes.

FIG. 2 is an explanatory diagram of path metric normalization, and curve a
shows an example of the path metric when normalization is not performed, Δ is the increase/decrease width of the threshold, and the threshold is Δ, 2Δ, 3
Δ゛, . . . are increased in response to an increase in the path metric. As mentioned above, when searching for a forward path, the current path metric is the result of adding the previous path metric and the current branch metric, so the path metric changes according to the path depth according to curve a. As shown, it will gradually increase.

In the present invention, normalization is performed using a threshold value Δ. For example, since the path metric is equal to or greater than the threshold value 6 at the path depth nl, it can be determined using the sign bit. In that case, the path metric normalized by the modulo calculation by the calculation unit 5 is selectively output. Therefore, the path metric is shown in the song vAb, and can be expressed using a small number of bits.

At path depths n2 to n3, as shown in curve a, the path metric becomes equal to or greater than the threshold value 5Δ, and then reaches the threshold value 6Δ.
It does not exceed the threshold value of 5Δ, but falls below the threshold value of 5Δ. In the song yAb, the path metric is 0 at the path depth n3.
The following is true. This can be determined by the sign bit. In that case, the path search will be performed by retreating.

Then, when retreating to the path depth nt, the threshold value is lowered, and in the present invention, the first adder 1 adds the threshold value Δ to the previous path metric. In FIG. 2, as shown by the retreating arrow, the path retreats to the depth n2, resulting in a path metric shown by curve C.

The threshold value Δ is lowered and the process moves to forward path search.
At the path depth n4, the path metric is equal to or greater than the threshold value Δ, so normalization is performed as described above.

Furthermore, even when backward path searching and forward path searching are repeated, path metric normalization and threshold change control are performed, making it possible to reduce the number of bits for path metric calculation. , the circuit scale can be reduced. Moreover, the first and second adders 1. shown in FIG. 3. The functions of the subtracter 2, the arithmetic unit 4, the path determination unit 6, etc. can also be realized by the arithmetic functions of a microprocessor under program control.

〔Effect of the invention〕

As explained above, according to the present invention, the path metric is normalized by the calculation unit 4 during a forward path search, and the threshold value is lowered by the first adder 1 during a backward path search. Path metrics can be output.

Therefore, since it is possible to reduce the number of operation bits, the circuit scale can be reduced. Furthermore, since the amount of calculations is reduced, there is an advantage that high-speed processing is possible.

[Brief explanation of drawings]

FIG. 1 is a functional block diagram of an embodiment of the present invention, FIG. 2 is an explanatory diagram of path metric normalization, and FIG. 3 is an explanatory diagram of the Fano algorithm. 1.3 are first and second adders, 2 is a subtracter, 4 is an arithmetic unit, 5 is a selector, 6 is a path determination unit, and 7 is a path metric register.

Claims (1)

[Claims] In a sequential decoder based on the Fano algorithm, a first adder (1) that adds a path metric and a threshold value.
a subtracter (2) that subtracts a backward branch metric from the path metric; a second adder (3) that adds the path metric and the forward branch metric; an arithmetic unit (4) that performs a modulo calculation on the output by the increase/decrease width of the threshold value, the path metric, and the first and second adders (1
), (3) a selector (5) that selects and outputs the output of the subtracter (2) and the arithmetic unit (4); A sequential decoder comprising: a path determination section (6) that controls the selector (5) according to an output.