KR100360926B1 - Improved ACSU structure in viterbi decoder apparatus - Google Patents

Abstract

The present invention relates to an improved addition-comparison-selection unit (ACSU) logic circuit in a Viterbi decoder device and to prevent a malfunction due to overflow of a path metric in a Viterbi decoder. It is an object of the present invention to provide an ACSU logic circuit having an improved structure that performs stable operation using a rescaling circuit, and a rescaling technique that performs ACSU operation without rescaling circuit by increasing the number of bits of two's complement code and path metric.

According to the configuration of the present invention, in the Viterbi decoder device, an incorrect metric value is obtained due to an overflow in the process of adding the branch metric value from the branch metric unit 2 to the existing path metric value in the ACSU (5). In order to prevent it from being found, the circuit consists of an overflow detection circuit that performs a path metric rescaling operation, a multiplexer 8, and a metric rescaling adder 6. In addition, the two-complement metric rescaling system uses metric bits that are sufficiently larger than the operating range of the difference between path metrics in each state, and uses a signed two's-complement operation to perform comparison operation in ACSU without additional metric rescaling circuit Can be implemented using only a subtractor.

Description

Viterbi decoder apparatus having a plus-compare-selection unit circuit for performing a rescaling operation to prevent an overflow of a path metric value.

The present invention relates to a logic circuit for performing a metric rescaling operation for preventing an overflow of a path metric of an ACSU logic circuit in a Viterbi decoder device. The present invention relates to a metric logic system comprising only a simple overflow detection circuit and a metric rescaling circuit. It is an object of the present invention to provide a rescaling technique that uses a scaling logic circuit and signed two's complement operation and replaces a comparator with a subtractor to perform normal add-compare-selection unit (ACSU) operation without additional metric rescaling circuit. have.

In the Viterbi algorithm, the path metric value continues to increase, so that finite memory cannot continuously perform normal operations. For this reason, in the conventional Viterbi decoder device commercially available, many methods have been used in which a metric value is set to a real number and a metric is expressed by using a decimal point method or a scale is set as an integer. For example, in the real expression method, the metric is displayed using the floating point operation using the exponent part and the mantissa part to perform normal ACSU operation, or each time using a fixed point operation, or We have used a method of renormalization when overflow occurs outside the operating area. Also, in the case of integer expression, various methods are proposed based on the principle that the operation of ACSU in Viterbi algorithm is determined by the relative difference between the metric values and not the absolute value of the metric. A method of lowering a metric value by selecting a minimum metric among metrics of each state and subtracting the minimum metric value from all state metrics has been used. However, when manufacturing Viterbi decoding device in this way, a large number of comparators are used to manufacture the minimum metric selection circuit, which occupies a large silicon area when manufacturing with VLSI, which is the maximum factor of time delay in ACSU part. It is a factor that makes high-speed operation of the Viterbi decoder difficult.

Accordingly, the present invention proposes a metric rescaling structure for the development of a Viterbi decoder for use as a single integrated circuit or as an internal block in a multi-functional communication integrated circuit, and the branch metric value passed through a branch metric unit (BMU). In addition to this path metric, the metric rescaling circuit using the simple overflow detection circuit and the efficient structure adder and the path metric bit are increased by one bit to prevent the overflow of the metric value generated in the process of creating a new path metric. By using the complementary operation and the signed subtracter circuit, the metric rescaling operation of the ACSU, which is the largest part of the time delay in the Viterbi decoder, can be performed quickly and with fewer logic circuits, resulting in high efficiency and high speed operation. Made it possible.

1 is a general overall Viterbi decoder hardware configuration diagram

2 is a structural diagram of an ACSU that performs addition and comparison operations without a malfunction by using a two's complement operation in the Viterbi decoder device of the present invention.

3 is a logic circuit diagram of an ACSU rescaling a metric using an unsigned algorithm in the Viterbi decoder device of the present invention.

4 is an adder circuit of an ACSU logic circuit using an unsigned calculation method of the present invention.

<Explanation of symbols for main parts of drawing>

1: input serial / parallel converter 2: branch metric unit (BMU)

3: Partial Metric Unit (PMU) 4: Survival Memory Unit (SMO)

5: Add-Compare-Select UNIQ (6, 6A, 6B): Adder 7: Subtractor

8: Multiplexer (MUX) 9, 9A: Logic (AND) Gate

10: Logic Gate (OR) 11: Comparators 12: Register

13,13A, 13B: Adder 14: Adder

Referring to the configuration and operation of the present invention in detail as follows.

FIG. 1 is a block diagram of the overall Viterbi decoder hardware. An input serial / parallel converter 1 receiving serial inputs and outputting parallel outputs in consideration of an encoder's code rate, inputs at each branch (branch). A branch metric unit (2), which is a unit for obtaining a branch metric compared to an encoder output according to an encoder state, and a partial metric unit (3) storing metric, each Survivor Memory Unit (4), which remembers the most decoded path for each state, calculates and compares partial metric values coming into each state when transitioning from one state of Viterbi decoder to the next. It consists of an Add-Compare-Select Unit (5) for selecting.

FIG. 2 is a block diagram of an ACSU 5 which performs addition and comparison operations without a malfunction by using the two's complement operation in the Viterbi decoder device of the present invention. The path metric value is added to the adder (6) (6A) for generating candidates for the new metric and the subtractor (7) for comparison using the subtractor to compare the candidate values for the path metric of the next state. It consists of a multiplexer (MUX) 8 circuit for selecting a metric value. It expresses branch and path metrics in signed two's complement form and assigns enough bits to the path metric to have a dynamic range of more than twice the maximum value of the actual path difference. -The structure of the ACSU 5, which does not require additional metric rescaling circuitry in the system by performing a normal comparison operation in the selection unit (ACSU) 5. This structure is a conventional addition-compare-selection unit (ACSU) ( 5) replaces the comparator circuit for comparing the magnitude of each component required for the operation with the subtractor (7) circuit and ignores the overflow of the subtractor (7) and selects the most significant bit (sign bit) of the result. The multiplexer 8 can be connected to select a path.

As an embodiment according to the configuration of the ACSU 5 which performs addition and comparison operations without malfunction by using the two's complement operation method as described above, the subtractor 7 as shown in FIG. The most significant bit of) is directly connected to the input of the multiplexer 8 so that when the most significant bit is 0, A is selected as a survival metric and B is selected as a survival metric.

3 is a block diagram of an ACSU 5 logic circuit that performs a metric rescaling operation using only a simple overflow detection circuit and an adder while using an unsigned calculation method of the present invention, wherein the ACSU circuit is a path metric of each state. When no signal is generated depending on whether or not the AND (9) gate, OR (10) gate, and overflow detection signal are used to detect the overflow obtained by comparing the highest value with the given reference value. When the overflow detection signal is 0, a multiplexer 8A which selects a signal for subtracting a value of a certain constant value, a branch metric, a path metric, and a three-input adder 6B that adds the value passed through the multiplexer are newly generated. The comparator 11 for comparing the candidate path metric values, and the candidate path metric selected by the result of the comparator 11 to the new metric. The key consists of a multiplexer 8A. The circuit for detecting the overflow is the value at which the overflow is detected by subtracting the maximum value of the branch metric from the maximum value of the operating area or a smaller value below this value. . This will subtract the constant value in the next cycle to avoid overflowing the path metric value.

Therefore, the upper bit portion of the path metric is grouped by the logical product (9) to create a circuit for making an overflow detection of any one state. And the detection circuit of each state is connected to the logic sum 10 circuit, and generate | occur | produces the overall overflow detection signal. The generated signal is connected to the control signal of the multiplexer 8B so that a constant value, which is subtracted at the time of detection (logic 1), enters the adder 6B, and if it is not detected, the value 0 is input to the adder 6B. Will enter. On the other hand, the adder 6B performs an addition operation between the subtracted constant value (or zero value), the branch metric, and the path metric. That is, a simple overflow detection circuit and an adder while using the unsigned calculation method of the present invention described above. The ACSU (5) logic circuit which performs metric rescaling operation using only the bay detects the overflow through the overflow detection circuit and uses this signal as a control signal of the multiplexer 8A to use a constant value or a value of zero. Subtraction and the branch metric and path metric enter the input of the 3-input adder 6B to provide a way to perform the metric rescaling operation.

4 illustrates the above process in detail as an ACSU logic circuit using the aforementioned unsigned calculation method. In the first stage, a complete adder 13 exists as many as the number of bits. The complete adder 13 contains a constant value and a branch metric path metric so that the generated value becomes the input of the (metric number of bits-1) -bit adder of the next step. The adder 13 of the next stage is divided into upper and lower parts. On the upper result side, two separate adders 13A and 13B perform the add operation by presuming the carry to 1 and 0, and carry the lower result side. The low multiplexer 8C has a structure for selecting the correct result among the upper adders 13A and 13B. Such a structure can reduce the delay time caused by the adder of the existing ACSU. Thus, the present invention uses a logical multiplication circuit (9) and a circuit for detecting a single overflow of each path metric and the logical sum circuit. (10) has an overflow detection circuit which performs an overall function of detecting an overflow, and an adder circuit which adds a constant or zero value, a branch metric, and a path metric for rescaling according to the result signal. In order to perform the three-input add operation as shown in Fig. 4, the circuit is connected to the first full adder 13 and the next step uses the adders 13A, 13B, and 13C of the (metric number of bits-1) bits. The adder is added to the bottom end 13C and the top end 13A and 13B at the same time, and the adder uses two adders 13A and 13B to estimate the carry value of 0 and 1 in advance. And an addition carry value by the adder ahraetdan (13C) is a structure that selects the calculation result with the correct estimation value by the multiplexer (8C).

As described above, the present invention provides a metric rescaling structure and a logic circuit according to the development of a Viterbi decoding device. First, using a two's complement operation and increasing a bit allocated to a metric by one bit and using a subtractor as a comparator. In the ACSU structure, since the normal operation without the malfunction due to the overflow is performed without the need for an additional metric rescaling circuit, the circuit is simplified and the time required for the ACSU in the Viterbi decoding device is actually reduced. Next, the ACSU circuit, which uses a simple overflow detection circuit and a metric rescaling structure using an adder, uses a simple overflow detection circuit, a multiplexer, and a three-input adder to achieve low latencies and optimal bits. Perform the scaling operation. Therefore, it is possible to increase the speed of the metric rescaling part of the ACSU, which has the most time delay while maintaining the normal operation in the actual Viterbi decoding device, and to reduce the complexity.

Claims (5)

In the Viterbi decoder device, the branch and path metrics are represented in signed two's complement form, and the overflow operation is performed by assigning a sufficient number of bits to the path metric so as to have a dynamic range of more than twice the maximum value of the actual path difference. Overloading of path metric values, characterized by the structure of the ACSU 5, which does not require additional metric rescaling circuitry in the system while performing normal comparison operations in the add-compare-selection unit (ACSU) 5 even if it occurs. Viterbi decoder device with plus-compare-selection unit circuit for performing rescaling operation to prevent flow 2. The most significant bit (sign bit) of the result according to claim 1, wherein the comparator circuit of the add-compare-selection unit (ACSU) 5 is replaced with the subtractor 7 circuit and the overflow of the subtractor 7 is ignored. Viterbi decoder having an add-comparison-selection unit (ACSU) device configured to select a path by connecting to a multiplexer 8 for selection In Viterbi decoder device, overflow detection circuit detects overflow and uses this signal as a control signal of multiplexer 8A to subtract a constant value or zero value, and this value, branch metric, and path. Viterbi decoder device with an add-compare-selection unit (ACSU) circuit characterized by a method in which a metric enters an input of a three-input adder 6B and performs a metric rescaling operation. 4. The circuit according to claim 3, wherein the circuit for detecting a single overflow of each path metric using the AND circuit 9 and the over performing the function of detecting the overflow as a whole using the OR circuit 10 Viterbi decoder device having a plus-compare-selection unit (ACSU) device characterized by a flow detection circuit and an addition circuit for adding a constant or zero value for rescaling according to the resultant signal and a branch metric and a path metric. 5. The method according to claim 4, wherein the first stage is connected to the complete adder 13 and the next stage uses the adder 13A, 13B, 13C of the (metric bit number-1) bit to perform the three-input add operation. The adder is added to the bottom end 13C and the top end 13A and 13B at the same time, and the adder is estimated by using two adders 13A and 13B to estimate the carry values of 0 and 1 in advance. A Viterbi decoder device having an adder circuit for selecting a result calculated by the multiplexer 8C with the correct estimated value by the carry value of the lower adder 13C.