JPS62161231A - Communication control equipment - Google Patents

Abstract

PURPOSE:To allow the titled equipment to cope with data transmission by reading a data stored in a fixed length buffer at reception when an effective bit length of a variable length buffer is maximum, and minimizing the effective bit length of the variable length buffer at transmission when the data is stored in the fixed length buffer. CONSTITUTION:A bit data RD1 of each channel is stored once in the variable length buffer 10 at reception and sent to a communication control processing section as a data RD2 at the reception. On the other hand, an X-bit data included at each frame by 1-bit is stored in the fixed length buffer 11 at each occasion, a changeover switch 14 is turned to the position (b) at each processing unit and the information of X-bit is outputted as a consecutive bit data. A transmission buffer section 8 applies control to send the X-bit information stored once in the fixed length buffer 12 as X-bit at each frame at the transmission, the channel data is stored tentatively in the variable length buffer 13 and a transmission data SD2 is sent in the reverse operation as the reception. Thus, the X-bit information transfer is attained.

Description

[Detailed Description of the Invention] [Overview] In a system that accumulates signals transferred bit by frame and processes them as multiple bits of information, conventionally, the information is processed within the signal time of one bit. There was a problem that a high-speed processing device had to be used because of the need to perform this processing, but in order to solve this problem, the signal that is transferred one bit at a time in each frame was processed up to the number of bits in the processing unit. Accumulate on the sofa! In addition to serially sending this to the 7th frame, the information consisting of consecutive multiple bits in the frame transferred during this time is buffered using a variable length buffer whose effective bit length is dynamically controlled. and rearrange the input into information units. : discloses a control method that makes it possible to perform 91Fli without using a particularly high-speed processing device.

[Industrial Field of Application] The present invention relates to the control of a communication control device, and particularly when a single high-speed digital data line is used to form a frame consisting of a plurality of logical lines (channels) and perform data transfer. A single bit added to each frame (
The invention relates to control that allows easy processing of information transfer using a signal (hereinafter referred to as X bit).

[Prior Art] Fig. 4 is a diagram showing an example of a data frame on a high-speed digital line, in which (a) shows the state of one frame, and (b) shows the state of X bits and one channel. , (C) shows a set of X bits.

As shown in FIG. 4(a), a frame 1 is composed of one X bit 2 and a plurality of slots 3. Each slot 3 forms a time-division channel.

The number written inside each slot 3 in the figure represents the channel number, and the number at the top represents the number of bits, where X bit is 1 bit and each slot 3 is 8 bits. So there are 24 channels, so a total of 192
This indicates that it is a bit. (b) is an enlarged view of one slot, showing that one channel consists of 8 bits. The numbers O to 7 displayed within each bit 4' section are bit numbers.

A method as shown in FIG. 4(c) has been proposed as one method of transmitting information using the X bits sent one bit per frame. That is, (c) shows the X bits of multiple frames, where synchronization information F is provided for every 24 frames, and every other X bit between the synchronization information F is used as data D (Fig. (X bits with a middle - are displayed are undefined). For example, when data is being communicated via a digital communication network, and one terminal wants to switch the connection partner, the X bit can be used to communicate with an exchange within the digital communication network. and so on.

[Problem to be solved by the invention 1 In a communication control device, when processing data of each channel sent serially on a transmission path, each time the data is processed in units of processing (for example, 1 byte). Since this is processed (assembling and disassembling characters, etc.), it is sufficient to perform this processing before the next 1 byte of data is received.

For example, when the data transfer rate is 1.5 megabPS, the allowable processing time is 5.33 microseconds.

However, when considering the case of processing information using the aforementioned X bits, the time allowed for the processing is only the time for the data width of 1 bit. For example, in the case of a transfer rate of 1.5 megabPS, only 066 microseconds of processing time is given. Therefore, it is possible to use conventional communication control equipment as it is in terms of processing speed.If you want to realize a communication control equipment that can handle information transfer using X bits, you will need to use high-speed logic elements and line processing. The problem is that it is extremely difficult to make the device economical because of the complexity involved.

SUMMARY OF THE INVENTION In view of the above-mentioned conventional problems, an object of the present invention is to provide a control method that can easily handle data transfer using X bits using a communication control device having a processing speed that is commonly used.

[Means for Solving the Problems] According to the present invention, this object is achieved by providing a plurality of sets of logical channels 7j each consisting of a plurality of serial bits in a 2:74 column, as described in the claims. A time-division multiplex line is connected in which bits are added to form one frame, and the frame is transmitted through one physical line at regular intervals, and digital data can be sent and received between the lines. In the communication control device to be controlled, the fixed-length multi-bit buffer for storing the single-bit information and the maximum length for storing information on the mJ logical channel are the same as the fixed-length buffer. A variable-length buffer is provided that updates the effective bit length in synchronization with the data format on the line, and when receiving data, the data stored in the fixed-length buffer is read out when the effective bit length of the variable-length buffer is maximum. This is achieved by a communication control device that performs control so that the effective bit length of a variable length buffer is minimized when data is stored in a fixed length buffer during processing and transmission.

[Embodiment] FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, in which 5 is a DStJ, and 6 is a block diagram in which data (RDI) and clock (CLK) are separated from a received signal R sent from a DSU5. 7 is a reception buffer section, 8 is a transmission buffer section, and 9 is a communication control processing section. represents.

The reception buffer section 7 has a configuration as shown in FIG. 2(a), in which 10 is a variable length buffer;
11 represents a fixed length buffer, and 14 represents a changeover switch.

The transmission buffer unit 8 has a configuration as shown in FIG. 2(b), in which 13 is a variable length buffer;
12 represents a fixed length buffer, and 15 represents a changeover switch.

To explain the case of seven receptions using Fig. 2(a),
The bit data RD1 of each channel is stored in a variable length buffer 10.
is temporarily held, then the RD
2 to the communication control processing section. On the other hand, X-bit data, which includes 1 bit for each frame, is accumulated in the fixed-length buffer 11 each time, and when the processing unit (1 byte) is reached, the selector switch 14 is switched to the b side and the X-bit information is stored in consecutive bits. Output as data. During this time, the variable length buffer 10 expands the effective bit length and accepts the subsequent input data RD1 (channel bit data), and as soon as the X-bit accumulated data is sent out, the changeover switch 1'4 is set to a. The channel data is sent again.

By repeating this operation, the data that is transferred is divided into 1 bit per frame by the X bit and rearranged as information (1 byte) of continuous bits in the same way as bit data of a normal channel. and sent to the communication control processing section 9 as RD2.

In the case of transmission, the transmission buffer section 8 controls the information for X bits stored at one time in the fixed length buffer 12 to be transmitted as X bits for each frame, and temporarily holds the channel data in the variable length buffer 13. As a result, the transmission data SD2 is sent out by an operation opposite to that in the case of reception described above.

FIG. 3 shows an example of the configuration of a variable length buffer, in which 16 represents a shift register, 17 a counter, and 18 a selector.

In FIG. 3, the counter 17 is a 3-bit octal counter that counts n! from the received signal. It is incremented by the received clock and returned to zero by the synchronization signal in the frame. The selector 18 selects a storage element that outputs data according to the value of the counter 17, thereby making the effective bit length variable.

[Effects of the Invention] As explained above, the communication control device of the present invention accumulates the data transferred one bit for each frame during reception and delivers it to the communication control processing section after forming a continuous bit string in units of processing. Furthermore, during transmission, the data processed as a continuous bit string is decomposed and controlled to be inserted into the frame one bit at a time, so sufficient processing time is always provided, which makes it easier to implement the device. There is no need to use high-speed logical operation elements, and the line processing is simple, so it is possible to economically realize a communication control device that can handle X-bit information transfer, which has great consequences.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a diagram showing the configuration of a reception buffer section and a transmission buffer section, and FIG. 3 is a diagram illustrating an example of the configuration of a variable length buffer. Fourth
The figure shows an example of a data frame on a high-speed digital line. 1...Frame, 2...X bit, 3...Slot, 4...Bit, 5...DSU, 6...Line support section, 7...Reception buffer section, 8... - Transmission buffer section, 9... Communication control processing section, 10.13... Variable length buffer, 11.12... Fixed length buffer, 14.1
5... Selector switch, 16... Shift register, 1
7...Counter, 18...Selector agent Patent attorney - σ Block 2 1 diagram showing the 4 precepts of the present invention (a) (b)
Receive buffer section and transmitter
2 Figure

Claims (1)

[Claims] A time division multiplex system in which one frame is formed by adding a single bit to multiple sets of logical channels consisting of multiple bits in series in time series, and the frame is transmitted using one physical line at a constant period. A communication control device that connects a line and controls the transmission and reception of digital data between the lines, a plurality of fixed-length buffers of multiple bits for storing the single-bit information, and a part for storing the information on the logical channels. A variable length buffer whose maximum length is the same as that of the fixed length buffer and whose effective bit length is updated in synchronization with the data format on the line is provided, and when receiving, when the effective bit length of the variable length buffer is the maximum, the fixed length buffer is used. 1. A communication control device that reads and processes data stored in a fixed-length buffer, and performs control so that the effective bit length of a variable-length buffer is minimized when data is stored in a fixed-length buffer during transmission.