JPS62160530A - Data processor - Google Patents

Abstract

PURPOSE:To operate data repeatedly in continuous cycles by providing a latch, where the operation result in the preceding cycle is held, between a memory device and an arithmetic unit for pipeline processing. CONSTITUTION:In the latter half of a cycle 1, data is read out from the memory device 1 and is held in a latch 5. In a following cycle 2, the arithmetic unit 3 uses data held in the latch 5 to perform the operation, and data used for the following operation is read out from the memory device 1 and is held in the latch in the latter half of this cycle 2. If data used for the following operation is the operation result in the cycle 2, data read from the memory device 1 is invalidated, and the operation result is taken into the latch 5 in the latter half of the cycle 2. In a cycle 3, data held in the latch 5 is used to perform the operation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing device that processes data in a pipeline method.

[Conventional technology]

Section 6 is a block diagram showing the configuration of the conventional data processing equipment in this building. In the diagram, (1) is the device that stores the data to be processed, (2) is the data output route, <sr
is the storage device (1) read out via the indulgence path (2)
(4) is an arithmetic device that processes the data of this arithmetic device (
The bud paths for writing the calculation results in step 3) into the storage device (1) are shown.

The operation of this data processing device is shown in the time chart t in FIG.
0, which will be explained below with reference to RDn (
n=1.2.5...) is the data read timing from the storage device (1), OPn (n=1.2.3.
) is the calculation timing of the calculation device (8), w T n
(n = 1, 2, 3, ·Φ·) respectively indicate the timing of computation of the calculation result to the storage device (1).

Here, the arithmetic unit (3) performs operation 1, operation 2, and operation 31a next'+IIF. Of these, in operation 1, all data is read from the storage device (1) at the timing of RDi in the second half of cycle 1, and after all calculations are performed at the timing of OPl in cycle 2, the calculation results are obtained at the timing of WTI in the first half of cycle 6. Also, in operation 2, RD2. which is one cycle later than this is stored in the storage device (1). OF2. WT2
At the timing of 0, the same calculations, calculations, and insertions are performed, respectively.Furthermore, in operation 6, RD3, which is one cycle later than operation 2, is executed. OF2. Similar reading, calculation, and writing are performed at the timing of WT3.

In this case, in the second half of cycle 2, the arithmetic unit (8) simultaneously performs the operation 1 (OPl) and the read operation 2 (RD2), while in the first half of cycle 5 the operation 1 writes (WTl). The operation 2 calculation (OF2) is performed simultaneously to improve the performance of the system.

[Problem that the invention seeks to solve]

A conventional data processing device is configured as described above.
For example, if the next operation is to be performed using the result of operation 1, operation 1 and operation 5tl- will be executed, and another operation will be performed in operation 2.

In other words, when processing certain data repeatedly, after the calculation, it is necessary to write to the storage device and remove the data from the storage device. The problem was that it couldn't be done.

This development 11111 was made in order to solve the above-mentioned problems, and its purpose is to obtain a data processing device that can perform repeated operations on data in consecutive cycles.

[Means for solving problems]

A data processing device according to the present invention provides a latch between a storage device for pipeline processing and an arithmetic device, causes the latch to hold data indicating an arithmetic result of the previous cycle of the arithmetic device, and the arithmetic device The data held in this latch is used to perform calculations.0 [Operation] In this invention, data indicating the calculation result is taken into the latch, and the data held in this latch is transferred to the calculation device. By using this as input data, it is possible to perform repeated operations on the data in consecutive cycles.

[Implementation - Examples]

One＼ Figure 1 is a block diagram showing the configuration of one embodiment of the present invention. In the figure, the same reference numerals as in Figure 6 indicate the same elements, and other than these (6) Storage device (1
) and the arithmetic device (8), which holds data read from the storage device (1) and stores the data read out from the storage device (1).
8), data indicating the calculation result is taken in, and the data held here is used as the input data of the calculation device (3).0 This embodiment configured as described above. The operation will be explained below with reference to the time chart of FIG.

First, when data is read from the storage device <1>, this data is held in the latch (5), and the arithmetic unit (8) uses the data held here to perform 4. I do. Further, data indicating the calculation result is written to the storage device M(1), thereby performing data processing similar to that shown in FIG.

Next, when performing calculations again using the results calculated by the calculation device (3), data is read from the storage device fit (1) at the timing of RDl in the latter half of cycle 1, as shown in FIG. Data is held in latch (5). The calculation device (8) performs calculation at the timing of OP1.

At this time, if the data calculated at the timing of OF2 of cycle 6 is the result of the calculation performed at the timing of OPl, reading out the data from the storage device (1) is disabled and the result of the calculation performed at the timing of opl is It is taken into the latch (5) at the timing of LOH. Arithmetic unit (8) is OF
Calculation is performed at timing 2. Also, the timing of LOH and OF3, which is one cycle later than this, is
After g, import into the latch (6) and perform all calculations. Note that when it is necessary to store the calculation result in the storage device (1), the WT 1. Cycle 4 w'r2*・
You can memorize it at the timing of ・.

Thus, according to this embodiment, data can be repeatedly operated in consecutive cycles.

〔Effect of the invention〕

As explained above, in this invention, a latch is provided between a storage device for pipeline processing and an arithmetic unit, and this latch holds the arithmetic result of the previous cycle of the arithmetic unit as input data to the arithmetic unit. Therefore, data can be repeatedly operated on in successive cycles, which enables high-speed data processing.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.
FIG. 2 is a time chart for explaining the operation of the same embodiment, FIG. 3 is a block diagram showing the configuration of a conventional data processing device, and FIG. 4 is a time chart for explaining the operation of the same device. . (1): Storage device (8): Arithmetic device (6) Two launches Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] A latch capable of holding data indicating the calculation result of the previous cycle of the calculation device is provided between the storage device for pipeline processing and the calculation device, and the calculation device uses the data held in the latch. A data processing device characterized in that it performs arithmetic operations.