JPS6215957B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit for stably performing a write operation of an electrically writable nonvolatile memory element.

Conventionally, a write circuit using two or more electrically writable nonvolatile memory elements has a circuit configuration as shown in FIG.

Although the drawings will be explained, all subsequent explanations will be based on an n-channel transistor as an example.

Insulated gate field effect transistor (hereinafter referred to as
(referred to as IGFET) M1 has a configuration in which the write power supply V _P is the drain, the write signal V _W is the gate, and the digital line D to which the memory element is connected is the source.
Memory elements M2 and M3 each have a common drain and are connected to digital line D, gates are connected to memory element selection signals V _A and V _B , respectively, and sources are grounded. Writing is performed when the write signal V _W is at a high level, ie, "High", and writing is not performed when the write signal V W is at a low level, ie, "Low". When V _A or V _B is "High", writing to memory element M2 or M3 begins.

If you write at the timing shown in Figure 2,
At write time _t1 , selective writing is performed on memory element M2, and at writing time _t2 , selective writing is performed on memory element M3.

Changes in the potential V _D of the digital line are initially GND
When the (ground) potentials V _W and V _A are applied to “High”, they rise to the voltage determined by the resistance ratio of M1 and M2, and this starts writing to M2, and electrons are written to M2 and sent to the floating gate. is injected, the threshold voltage V _TM2 rises, and the potential V _D of the digital line rises.

Next, when M3 is selected, the initial threshold voltage V of M3
The potential drops once due to _TM3 and the resistance ratio, and gradually rises as it is written.

The amount of shift of the threshold voltage V _TM of the memory element (the amount of change in the threshold voltage V _T after writing and at the initial stage) largely depends on the drain voltage. In such a conventional write circuit, as described above, the voltage of the digit line fluctuates greatly, so the characteristics (such as V _TM ) of the memory element after writing vary widely. This is particularly noticeable when the number of memory elements increases. This naturally causes variations in not only write characteristics but also erase characteristics.

As described above, the memory element using this write circuit has the drawback that the write characteristics and erase characteristics vary widely, and it is difficult to have stable and uniform characteristics.

The purpose of this invention is to clamp the digital line voltage at a certain voltage by using two depletion and enhancement type IGFETs, thereby realizing a memory element with stable and uniform write and erase characteristics with little variation. The purpose is to provide circuits.

According to the invention, an electrically writable
It has a plurality of IGFETs as non-volatile memory elements, the drain of each memory element is connected to a common digital line, the gate is connected to an address selection signal line, the source is connected to a common ground, and a write selection signal line connected to the digital line is connected. In the nonvolatile memory write circuit having a circuit, there is obtained a nonvolatile memory write circuit characterized in that a clamp circuit is connected to the digital line.

Next, one embodiment of the present invention will be described with reference to the drawings.

FIG. 3 is a circuit connection diagram showing one embodiment of the present invention, which includes a write selection IGFET M1 and memory elements M2 and M3.
It consists of a depletion type IGFET M4 and an enhancement type IGFET M5, the drain of M1 is the write power supply, the gate is the write signal, the source is the digital line, the drains of M2 and M3 are the digital line, the gate is the selection signal, and the source is grounded. M4
The drain is connected to the digital line, and the gate and source are connected to the M
Connected to the drain of No. 5, and its gate and source are grounded.

When M4 and M5 constitute a clamp circuit and write is performed at the timing shown in FIG. 4, selective writing is performed to memory element M2 at writing time _t1 , and selective writing is performed to memory element M3 at writing time _t2 . .

The potential of the digital line is initially GND potential, then V _W
When V _A is applied to "High", the voltage increases to the voltage determined by the resistance ratio of M1 and M2, and as the voltage of the digital line, which is also the drain voltage of M2, increases, writing to M2 starts and the flow of M2 starts. As electrons are injected into the counting gate, the threshold voltage V _TM2 rises, and the voltage on the digital line continues to rise.
At this time, since the gate of M5 is grounded, no current flows through M5. When the potential of the digital line and node E increases and the potential of E exceeds the drain breakdown voltage of M5, a current begins to flow through M5. At this time, the current value is determined by the size of the transistor M4. This current keeps the potential of the digital line almost constant, and since the maximum value of this potential is determined by the drain breakdown voltage of M5 and the characteristics of the transistors M4 and M5, it can be easily controlled in design or manufacturing.

Next, at time _t2 , when selective writing is performed on M3, the potential of the digital line drops once, but as in the case of M2, it gradually rises and becomes constant at a certain value.

In this way, the potential of the digital line is clamped to a predetermined value and becomes substantially constant, so that writing is performed in each memory element under substantially the same conditions, and the characteristics after writing are also substantially uniform.

Note that the clamp circuit may consist of only one enhancement type IGFET whose gate and source are commonly connected, or may include multiple IGFETs connected in series or parallel as necessary, or any other circuit that can clamp the IGFET to the desired potential. Needless to say. Further, the number of memory elements and the number of IGFETs constituting the write selection circuit may be arbitrary, and it goes without saying that the present invention can be applied to a circuit using P-channel type IGFETs.

As explained above, the write circuit of the present invention using a clamp circuit performs writing more stably than the conventional one, has uniform write characteristics and erase characteristics, has little overall variation, and has variable drain breakdown voltage. This has the advantage that writing characteristics and erasing characteristics can be easily controlled.

[Brief explanation of the drawing]

Figure 1 is a circuit connection diagram showing a conventional write circuit.
FIG. 2 is a time chart showing the write signal waveform of a conventional circuit, FIG. 3 is a circuit connection diagram showing an embodiment of the write circuit of the present invention, and FIG. 4 is a time chart showing the write signal waveform. Note that the broken line portion in FIG. 3 is a conventional write circuit. In the figure, M1, M5...enhancement type IGFET, M4...depletion type IGFET
IGFET, V _P ...Write voltage, _VW write selection signal, D...Digital line, V _A , V _B ...Memory element selection signal, M2, M3...Memory element.

Claims (1)

[Claims] 1 A plurality of electrically writable insulated gate field effect transistors are used as nonvolatile memory elements, and the drain of each memory element is connected to a common digital line, the gate is connected to an address selection signal line, and the source is connected to a common ground. In the write circuit for a nonvolatile memory having a write selection circuit connected to the digital line, the digital line is provided with a clamp circuit, and the clamp circuit includes a constant voltage element for determining a clamp voltage. Non-volatile memory write circuit.