JPS62155683A - Code converter - Google Patents

Abstract

PURPOSE:To edit a digital video signal freely by forming a writing designating code and a reading designating code respectively from a header identifying code of a header signal and a picture change over instruction code respectively. CONSTITUTION:A code converter 4 takes out the header identifying code 'B19A' and the picture change over instruction code 'B19B' from the header signal in the digital video signal. The codes 'B19A', 'B19B' of the header signal are respectively replaced by the designating codes 'B19W', 'B19R', respectively to form a new header signal. When the digital video signal has the header identifying code and the picture change over instruction code, the editing is performed. Thus, said both codes do not depend on the values of the header identifying code and the picture change over instruction code of the digital video signal of the preceding frame but is independent, so that the editing is freely carried out without receiving any restriction.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a code conversion device, which converts a header identification code and a screen switching instruction code provided in a header signal of a digital video signal into a writing designation code and a readout designation code, respectively. The present invention relates to a code conversion device that performs conversion.

Conventional technology Conventionally, an audio signal or an angle signal and a video signal are
Conventionally, discs have been widely known in which the respective signals are digitally modulated, synthesized in time series, and recorded on concentric or spiral tracks as, for example, changes in geometrical shape. This disc is called a digital audio disc because the recorded information is mainly an audio signal, and the video signal is mainly a still image and serves only as auxiliary information to help you imagine the name of the audio signal. ing. On the recording track of this digital audio disk, information signals such as audio signals and about 3,000 still images are digitally modulated, converted into a digital C8 format, and then frequency modulated and recorded.

It takes approximately 2.26 seconds to reproduce one screen's worth of zero mountain image information from the above disc. The playback device that plays this disc is equipped with video memory for two screens, and after all still images are written into one memory, the still images are read out from the other memory to one memory. By switching to , you can perform a cut operation that instantly rewrites the display screen.

Also, while loading the still image J1 into one memory, the still image is read out from this one memory, and a wipe change is performed in which the display screen is gradually rewritten.

Problems to be Solved by the Invention Each still image information recorded on a digital audio disc must be written to either the first or second memory, and simultaneously read from either the first or second memory. A specification code is added that specifies whether to perform the following.

However, if the order of each still image information when recording on a digital audio disc is changed due to editing work, one car that should perform a cut operation (or wipe change) will not be able to perform a wipe change (or cut operation). There are cases where this happens. This is because the designation code of each still image information designates the first or second memory, and the display switching of still images depends on the designation code of the preceding still image. For this reason, editing to change the recording order of each still image is restricted, and there is a problem in that the degree of freedom in editing is low.

Therefore, the present invention provides a code conversion device that solves the above problems by converting the header identification code and screen switching instruction code provided in header No. 4ii into a write designation code and a read designation code, respectively. The purpose is to

Means for Solving the Problems In the present invention, header signals in a digital video signal include those with still image information and those without. It represents. Further, a screen switching instruction provided in advance in the header signal indicates whether the display screen is to be cut or wiped. According to the header identification code and screen switching instruction code extracted from the above header signal, when the header signal does not include still image information and instructs cut switching, the readout specification code changes its value. generated. This readout designation code specifies the first memory or the second memory, each of which stores still image information for one screen, and specifies reading of still 1L image information from either of them. In addition, when the header signal includes still image information and instructs a cut operation, the write specification code is a value that specifies a memory different from the first read specification code, and in other cases, the write specification code is a read specification code. is generated as a value that specifies the same memory as . This read designation code designates the first memory or the second memory to designate writing of still image information accompanying the header signal.

Thereafter, the header identification code and screen switching code of the header signal are replaced with a write designation code and a read designation code, respectively.

In the present invention, a digital video signal whose header signal is provided with a header identification code and a double-sided switching code is edited by changing the order in units of still images. In the edited digital video signal, the header identification code and double-sided switching code of the header signal are replaced by a fortune-telling designation code and a readout designation code, respectively, by the apparatus of the present invention. Therefore, digital video signals can be edited freely without being restricted by designated codes.

Embodiment FIG. 1 shows a main part of the code conversion device according to the present invention.
! ! FIG. 2 is a block system diagram of an embodiment of a recording system of an information signal recording disk to which the apparatus of the present invention is applied.

In FIG. 2, the digital recorder 1 has a plurality of static I/Os.
A digital video signal of an arbitrary still image is recorded, and the digital recorder 1 reproduces a digital video signal of an arbitrary still image under the control of the editing control device 2 and supplies it to the digital recorder 3.

The digital recorder 3 records the digital video signals of the still images supplied to the digital recorder 1J in the order in which they are supplied. As a result, digital video numbers ζ of a plurality of still images are recorded on the digital recorder 3 in a desired order and edited.

Here, the digital video signals recorded on each of the digital recorders 1 and 3 have a signal format as shown in FIG. The digital video signal for one field includes 684 header signals shown as H1 to H684 in FIG. 3, and Yl, Y2, . . . (R-Y)1. (B-Y)1.
. . . After the digital video signal of each frame, components 1 to ? '3''I-! A header signal without an i-conversion signal is inserted. The above editing is performed in units of digital video signals for one frame, into which a header signal is later added.

First, to explain the component encoded signal,
Number of scanning lines: 625, horizontal scanning frequency: 15.625 k)
Of the color video signals for one frame of -12, only the signal for the video period is the luminance signal, which has a sampling frequency of 9M.
The two color difference signals (R-Y) and (B-Y) are each sampled at a sampling frequency of 2.25 MHz and quantized at 8 bits. Sampled and quantized. The digital luminance signal has 456 sample points (pixels) per scanning line, and has 572 effective scanning lines for one frame.

The above-mentioned digital luminance signal and two types of digital color difference signals are respectively written into a memory circuit (not shown), and further, by a readout control signal of a predetermined frequency, the digital luminance signal is converted to a sampling frequency of 88,2, 1''Z, quantum The two types of digital color difference signals are each read out at a sampling frequency of 8 bits, and each has a sampling frequency of 88.2 kl2.

The fi quantization number is read out with 8 bits and applied to a switching circuit (not shown). This switching circuit is supplied with a separately generated header signal with a sampling frequency of 44.1 kl-17 and a quantization number of 16 pits, and the switching circuit switches these input digital signals in a predetermined order to the third A digital video signal for one field having the signal format shown in the figure is generated and recorded on the digital recorder 1 shown in FIG. 2.

In FIG. 3, the digital video signal for one field consists of one word of 16 bits and 16 bits, and each word of digital luminance signal of 143 words! ? iY "Y45t3 'Digital color difference signal @ (RY) 1 ~ (RY) 114° (
B-Y) ~(B-Y) and 31684 header signals T1~[''684 of 6 words each, which are combined at the beginning position of each of these signals, are synthesized in chronological order. , a total of 101,916 words of digital signals.

143 transmitted next to the header signal @H1 shown in Figure 3
The word digital luminance signal Y1 indicates, for example, a total of 286 pixel data groups of the first field, as indicated by diagonal lines in FIG. Two pieces of pixel data are arranged in the lower 8 bits. Further, the 143-word digital luminance signal Y2 transmitted next to the header signal H2 has a total of 286 pixels in the second field, for example, as shown by diagonal lines in FIG. 2 in the second vertical column from the left on the screen. This shows a data group, and two pieces of pixel data are arranged in the 1st-order 8 bits of one word in the same way as above. Further, the digital luminance signal Y3 following the header signal H3 is the i+286 double-thread dank group of the first field in the third vertical column, and the digital luminance signal Y4 following the header signal H4 is the second field in the fourth vertical column. A total of 286 pixel data groups are shown in the field, and the digital luminance signal Y5 next to the header signal H7 is of the first field in the fifth vertical column.
? + Shows a group of 286 pixel data.

Furthermore, (R-Y) 1 next to the header signal H5 indicates a total of 286 pixel Y-ta groups of the first field, for example, in the first vertical column at the far left on the screen of the first digital color difference signal. (B-Y)1 following the signal H6 indicates a total of 286 pixel data groups of, for example, the first field in the first vertical column at the leftmost end on the screen of the second digital color difference signal. in this way,
Four columns of pixel data groups in the vertical direction of the digital luminance signal and two
The component encoded signal has a signal format that is transmitted in time series for each unit, with a total of six pixel data groups of one column of pixel data in the vertical direction of the seed digital color difference signal as the middle rank. , pixel data I of odd-numbered columns
! At tT, the pixel data group of the first field is transmitted, and for the even-numbered column pixel data group, the pixel data δT of the second field is transmitted and recorded in the digital recorder 1.

Next, signal format 1- of header signals H1 to H684
This will be explained in conjunction with FIG. Header signal H1-11
Each of 684 consists of 6 words. J3 is in Figure 4,
The vertical direction shows the bit array, with the upper part being the MSB (Morss 1 to
・Significant bit), the lower side indicates the LSB (lease [...significant bit), and the horizontal direction indicates the word, which is the same as in FIG. The first word of the header signal contains all 15 bits indicated by 5YNC.
1] and a transmission tunnel code shown under IP/Σ is placed in the l-S B 1 bit. The upper 2 bits of the second word are the image type identification code indicated by l' M O D E J, the 3 upper bits from the 3rd bit to the 5th bit are the special effect code rs and EJ, and the next 3 bits are the special effect code rs and EJ. Species identification code rP, GJ, 9th Pi 1-th "1"
" is a binary number "1", the 10th bit is the image information amount identification code, the 11th bit is the screen transmission identification code, and the 12th bit is the screen transmission identification code.
The 1st bit is the header identification code rB19AJ, the 13th bit is the screen switching instruction code rB19BJ, and the 14th bit to the 16th bit (lSB'') is a total of 3.
The bits are memory column discrimination codes r82 to BOJ.

Address code r83 to 81 of the upper 8 bits ΔDla of the third word and the upper 8 bits AD2a of the fourth word
8'' indicates the address of the memory where the pixel data of the upper 8 bits of the first word of the video signal section in the 625 scanning line system is stored, and the lower 8 bits AD1b, ΔD2b of the third and fourth words. address code f
'83-818' designates the memory address in the 525 scanning line system. Furthermore, the fifth and sixth words of the header signal are two spare words,
Usually it is all [01.

The above header identification code "B19Δ-1 is the value rOJ
Notogi so header G: ;' jj is a component]・
(11"1"1" indicates that the header signal is not accompanied by a component encoded signal and is inserted between each field.The screen switching instruction code rB19BJ is , a value of "0" indicates a wipe change in which both sides are gradually replaced, and a value of "0" is displayed.
1" instructs a cut change in which the cut display screen is instantly rewritten.

In other words, as shown in Figure 3, 1 Hetsuday No. 1-11~”684
The header identification code rB19A,I is directly set to [01. Further, the values of the double-sided switching instruction signals of the header signals H1 to H684 are the same for each field.

Returning to FIG. 2, the digital recorder 3 sequentially reproduces the digital video signals and supplies them to the code conversion device i\4. The code conversion device 4 converts the header signal J:reheader identification code r in the digital video signal.
B19AJ and screen switching instruction” - Take out the B19BJ. The extracted header identification code rB19AJ and screen switching instruction code r1319DI are supplied to terminals 20 and 21 of the circuit shown in the first diagram, respectively. The header identification code rB198J is supplied to one inverting input terminal of the AND circuit 22 and one input terminal of the AND circuit 23,
Double-sided switching instruction No. 111 1'B19BJ is AND circuit 23
is supplied to the other input terminal of the AND circuit 22 via the inverter 24. The output signal of the AND circuit 22 is supplied to one input terminal of an exclusive OR circuit 25, and the output signal of the AND circuit 23 is supplied to a clock input terminal of a D-type flip-flop 26. The flip-flop 26 is σ
The output terminal is connected to the data input terminal to form a T-shaped flip 70, and its Q output signal is supplied to the other input terminal of the exclusive OR circuit 25.

Here, the flip-flop 26 has a header identification code rB19AJ and a screen switching instruction code f'B19B.
Since the header signal is inserted between fields from each J, it is triggered only when a cut operation is instructed, and the value of the Q output signal is inverted. This Q output signal is output from the terminal 28 as a read designation code rB19RJ.

Since the exclusive OR circuit 25 includes a header signal with component encoding in each field,
Further, only when a cut operation is instructed, the read designation code rB19RJ output from the flip-flop 26 is inverted and output, and in other cases, the read designation code is output as is. The output of this exclusive OR circuit 25 is sent to the terminal 27 as a write designation code rr319WJ.
It is output from

The fortune-telling designation code rB19Wj specifies the fortune-telling of two memories in the playback device, which will be described later.
When OJ (or "1"), it instructs to write pixel data of a digital video signal into the first (or second) memory. The read designation code rB19RJ designates reading of the above two memories, and is [rO
J (or "1"), it instructs to read pixel data from the first (or second) memory. The designated code conversion device 4 converts these designated codes I'B19WJ, rB1
The header signal code rB19 shown in Figure 4 for each 9RJ.
By replacing each of AJ and rB19BJ, a new header signal shown in FIG. 5 is generated.

The header signals shown in FIGS. 4 and 5 are the same except for the designation codes rB19WJ and rB19RJ. The specified code conversion device 4 supplies a digital video signal having the header signal shown in FIG. 5 to the signal processing circuit 5.

In this way, a digital video signal is edited when it has a header identification code and a screen switching instruction code, and both of the above codes are the values of the header identification code and screen switching instruction code of the digital video signal of the preceding frame. Since it is independent and does not depend on , editing can be done freely without any restrictions. Also, old designation code.

Each read specification code is a header identification load.

A designation code is generated according to the value of each double-sided switching instruction code, and is used to switch the still image display according to the instructions of the double-sided switching instruction code.

Input terminals 6 and 7 receive analog audio signals of 2 channels separately, a start signal enters input terminal 8, and a music program of analog audio signals enters input terminal 9. A cue signal comes in every time there is a change from one program to another music program. Here, disk 14, which will be described later, contains information for one channel +ih
Assuming that the sampling frequency is 44.1 kl-1z, and the digital signals for 4116 bits of suspension are recorded on one track in time series for 411 channels,
The two channels of analog audio signals mentioned above are processed by the AD converter 10 so that each channel has a sampling frequency of 44.
1KH7t-sampled, converted into a 16-bit digital audio signal (PCM audio signal), and supplied to the signal processing circuit 5.

Further, a control signal generated by the control signal generation circuit 11 is supplied to the signal processing circuit 5. The control signal is used for position control (random access) of the pickup reproducing element, etc.

The signal processing circuit 5 receives a digital video signal in a signal format l- as shown in FIG. , and rearrange the parallel data into serial data.
The digital signals of each channel are divided into predetermined sections, and the signals are interleaved and time-division multiplexed.

- Then, a recording signal is generated by further adding an error code fixing signal, an error code detection signal, and a synchronization signal bit indicating the start of a block (frame).

FIG. 6 is a diagram schematically showing an example of one block (one frame) in the recording signal generated as a result of signal processing by the signal processing circuit 5, and one block is composed of 130 bits. 5YNC indicates the multiplexing position of the 8-bit fixed pattern synchronization signal indicating the beginning of the block, and Ch-1, Ch-
2 indicates the digital audio signals of the two channels, and ch-3 and Ch-It indicate the multiplexing positions of 16 bits and 1 word of the digital video signals of the two channels. Also, not shown in Figure 6, P and Q are people 16 bits 1~
This is an error code correction signal. Furthermore, CRCG is a 123-bit error code detection signal, Δdr is a control signal used for random access, etc., and L is a user's bit. It 130 from 5YNC to () not shown in Figure 6
One block of signals is composed of bits, and the digital signals are synthesized in the middle of this block at the same frequency as the sampling frequency of the digital audio signal, 44.1kl-1z, and are transmitted in time series. Lede
The disk 1 is recorded through a recording device 13 using a beam.
Recorded in 4.

This disk 14 has a signal format, not shown in FIG. A spiral main track recorded as a bit string and approximately in the middle between each track center line of adjacent main tracks, alternately every disk rotation period, within a band lower than the band of the frequency modulated wave. burst-like first and second bursts of a single frequency
Tracking control reference signals f, 1, and fP2 are recorded by intermittent bit strings to form a sub-1 rack, and a third tracking control reference signal is also formed on the main track at the switching connection portion of fPl and fP2. Signal fP3 is recorded. Further, this disk 11 does not have a tracking guide for the reproducing needle, and has an electrode function.

Next, a device for reproducing digital video signals recorded on the disk 14 will be explained using FIG. 7. In the figure, the disk 14 is rotated at a predetermined rotational speed, and a scanning needle 30 called a sensor slides and scans. By detecting the change in capacitance between the electrode of the scanning needle 30 and the bit string recorded on the disk 14, the green signal is reproduced and outputted by the pickup circuit 31 in a known manner. The output reproduction signal of the pickup circuit 31 is demodulated by the FM demodulator 32, and the demodulated digital signal extracted here is applied to the decoder 33, where the synchronization signal bit 5YNC1 is
This is a time-series composite signal consisting of two channel digital audio signals, two 1-channel digital video signals, an error code correction signal, and the like. Thereafter, the beginning of the signal block is detected based on the synchronization signal bit 5YNC, the serial signal is converted into a parallel signal, and error detection is performed. Only when an error is detected, correction IF restoration of error No. 15 is performed using the error code correction signal. In this way, two of the four-channel digital signals are corrected and restored as necessary, and are error-free and restored to their original order before interleaving.
The digital audio signals of each of the two channels are converted into analog audio signals by a DA converter in the decoder 11, and then outputted to output terminals 34 and 35, respectively. On the other hand, the digital video signals of the two channels are reproduced in time series, combined into a predetermined signal format with a header signal added for each pixel data group of 111 columns on the screen, and then supplied to the scanning line number conversion circuit 36. Here, it is converted to a system with 525 scanning lines. The output pixel data of the scanning line number conversion circuit 36 is sent to the switch circuit 3.
7, the signal is supplied to a first or second frame memory (hereinafter simply referred to as "memory") 43 or 44, which constitutes a main part of the apparatus of the present invention.

Further, the digital video signals sequentially extracted from the decoder 33 in time series are also supplied to a synchronization signal detection circuit 38, a header signal detection circuit 40, and a metric write controller 41, respectively. The synchronization signal detection circuit 38 detects the synchronization signal in the header signal and sends the detection signal to the control circuit 39.
supply to

Further, the header signal detection circuit 40 selectively reproduces each code and address signal other than the synchronization signal in the header signal and supplies it to the control circuit 39.

The control circuit 39 is supplied with the above synchronization signal detection signal and each code detection signal of the header signal, discriminates and decodes these input signals, and operates the scanning line number conversion circuit 36 and the switch circuit 37.
．． Memory write controller 41. Memory read controller 45. Controls the switching circuit 46 and the like. The memory write controller 41 writes pixel data in the digital video signal B supplied to the memory 43 or 44 to a predetermined address based on the address signal in the header signal. The switch circuit 37 selects the terminal a when the value of the code rB19WJ is "0" and selects the terminal a when the value of the code rB19WJ is "1-1" according to a control signal from the control circuit 39 based on the memory allocation designation code rB19WJ in the header signal. You can switch to select

As a result, pixel data is supplied to the first memory 43 or the second memory 44 designated by the code rB19WJ. The memories 43 and 44 read out one frame of pixel data based on the read control signal from the memory read controller [1-ra and the synchronization signal detection signal 45], and also correct jitter associated with reproduction. The pixel data read from each of the memories 43 and 44 is supplied to the switching circuit 46.

The switching circuit 46 receives the memory read designation code f'B19RJ1. in the header signal. : Based on the control signal from the control circuit 39, when the value of the code rB19RJ is "0", the output pixel data of the memory 43 is taken out, and when it is "1", the output pixel data of the memory 44 is taken out. and supplies the extracted pixel data to the D/A converter 47. The analog video signal D/Δ-converted by the D/A converter 47 is supplied to an encoder 48 . This ablog video signal is added with horizontal and vertical synchronization signals supplied from the memory read controller and the synchronization signal generation circuit 45, and is converted into a standard television system television signal and outputted from the output terminal 49.

Note that a header signal that is not accompanied by component encoded data can be inserted after the digital video signal of each frame when performing a cut operation, and this component encoded data is not accompanied when performing a wipe change. It is not necessary to insert a header signal, and the present invention is not limited to the above embodiment.

Note that the code conversion device 4 shown in the second figure is removed and the digital video signal is recorded on the disk 14 in the header signal format shown in the fourth figure, and the code conversion device is inserted into the header signal detection circuit 40 shown in the seventh figure. By providing a write designation code and a read designation code within the disk 14, the write designation code and the read designation code may be generated when the disc 14 is reproduced, and the invention is not limited to the above embodiment.

Effects of the Invention As described above, the code conversion device according to the present invention generates the 11 loading designation code and readout designation code from the header identification code and screen switching instruction code of the header signal, so that each of the displayed Cutting or wiping of still images is performed as instructed by the screen switching code, making it possible to freely edit the digital video signal provided with the header identification 1-code 1 screen switching instruction code, etc. It has the following characteristics.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of an embodiment of the main part of the device of the present invention, Fig. 2 is a block diagram of an embodiment of a disk recording system to which the device of the invention is applied, and Fig. 3 is an example of a digital video signal. FIGS. 4 and 5 are diagrams showing signal formats before conversion by the apparatus of the present invention. A diagram showing an example of the format of a header signal after conversion, Figure 6 is a diagram showing an example of the format of a 1-block signal recorded on a disc, and Figure 7 is a block diagram of an example of a disc playback system. It is a system diagram. 1.3...Digital recorder, 2...Editing control device, 4...Specified code conversion device, 5...Signal processing circuit, 14...Disk, 22.23...AND circuit, 24 ...Inverter, 25...Exclusi I
OR circuit, 26...flip-flop. Figure 1 Figure 4 Procedures available If official document February 12, 1986■ Director General Michibu Uga Display of 4 items 1985 Patent application No. 296896 Name of the invention Code conversion system 11 corrections 16 parties Sff Relationship with Patent Applicant Address: 3-12 Moriyacho, Kanayō-ku, Yokohama-shi, Kanagawa Prefecture 221 Name (432) Japan Victor Co., Ltd. Representative Director: Ai Shishi Michi-bu (Embedded Address: 102 Chiyoda-ku, Tokyo) Kojimachi 5-7-6
, the detailed description of the invention in the specification. 7. Correction details In aS, “read” in the first line of page 6 was changed to “write”
and correct it.

Claims (1)

[Claims] From the header signal in the digital video signal, extract a header identification code that indicates whether the header signal is accompanied by still image information, and a screen switching instruction code that instructs to change the display screen to cut or wipe. , the header identification code, and the screen switching instruction code, when the header signal accompanies still image information and instructs a cut change, the first memory and the second memory each store one screen worth of still image information. The header is generated by changing the value of a readout specification code that specifies reading of still image information from either one of the memories, and when the header signal includes still image information and instructs to change the cut. The write designation code that specifies whether to write the still image information accompanying the signal into the first memory or the second memory is a value that designates a memory different from the read designation code, and in other cases, the read designation A code converting device characterized in that the code is generated as a value specifying the same memory as the code, and the header identification code and screen switching instruction code of the header signal are replaced with the write specifying code and the read specifying code, respectively.