JP3214136B2 - Digital signal recording device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an 8 mm VTR, for example.
And a digital signal recording apparatus for recording an audio PCM signal on a magnetic recording medium by a rotating magnetic head.

[0002]

2. Description of the Related Art In an 8 mm VTR, as an audio recording mode, an AFM audio mode in which an audio signal is FM-modulated and frequency-division multiplexed between an FM-modulated luminance signal and a low-frequency conversion chroma signal for recording, and an extension of a video track. PCM to record digital audio signal on
There is an audio mode. The sampling frequency of the conventional audio PCM signal in the PCM mode is an integral multiple of the horizontal frequency fh, for example, 2fh (= 31.5 KHz).
Has been selected.

[0003] When the sampling frequency is set to an integral multiple of the video horizontal frequency, the rotating head rotating at the frame frequency and the sampling system are synchronized with each other, and the problem of out-of-sync between video and audio does not occur.

However, such a conventional 8 mmV
At a TR sampling frequency of 31.5 KHz, it is difficult to record and reproduce high-quality audio signals. In particular, with the advent of the Hi8 VTR, images have become higher in quality, and digital audio with higher sound quality corresponding to the higher quality has been desired. For that purpose, it is necessary to increase the sampling frequency. Further, since the sampling frequency of 31.5 KHz is different from the sampling frequency (44.1 kHz / 48 kHz / 32 kHz, etc.) employed in other digital audio devices, there is no consistency.

Therefore, as a sampling frequency of an audio PCM signal in an 8 mm VTR, a frequency (44.1 k) used in other digital audio equipment is used.
Hz / 48 kHz / 32 kHz, etc.) to improve sound quality and improve compatibility with other audio devices.

[0006]

However, the sampling frequency used in these other audio devices is, for example, the field frequency (59.
94 Hz). Therefore, when such a sampling frequency is used, there arises a problem that the number of sample data arranged in one field period does not become an integer. Therefore, in particular, audio P
When recording a CM signal, it is difficult to perform signal processing during reproduction as well as signal processing during recording. That is, if the number of sample data arranged in one field period is not an integer, it is necessary to reproduce a relationship that is not at an integer ratio during recording even during reproduction. If the ratio between the frequency of the recording reference signal and the audio sampling frequency is different from that at the time of recording, there is a problem that audio data becomes insufficient or excessive at the time of reproduction.

Accordingly, an object of the present invention is to provide a digital signal recording apparatus capable of recording and reproducing without any trouble even when the sampling frequency cannot be divided by the frequency of a recording reference signal, for example, the video field frequency.

[0008]

SUMMARY OF THE INVENTION The present invention relates to a digital signal recording apparatus for recording a digital information signal in which the relationship between the sampling frequency and the frequency of the recording reference signal is not an integer ratio. sample data number, the sampling frequency and recording groups
Sample calculated from the relationship with the frequency of the quasi-signal
Sample data number setting means for setting the number of sample data of a plurality of integer values close to the data number, and identification signal generating means for generating an identification signal for identifying the number of sample data of the digital information signal in each cycle of the recording reference signal equipped with a door,
The number of sample data in the cycle of the recording reference signal is
Calculated from the relationship between the recording frequency and the frequency of the recording reference signal.
This is a digital signal recording device that is made to correspond on average to the number of sample data to be obtained .

[0009]

In the case of the NTSC system, the field frequency is 59.94 Hz and the sampling frequency is 48.
In the case of kHz, the sampling frequency cannot be divided by the field frequency. That is, 48000 / 59.94 ≒ 800.8.

[0010] Numerical values that are integers of 2 or more close to this quotient, for example, 792 and 810 are set. Then, an identification information signal for identifying whether the number of samples of the digital information signal in one cycle is 792 samples or 810 samples is recorded.

Therefore, even if the number of samples for one field is an integer, the number of samples close to the quotient of the above-mentioned division is recorded on average. As a result, it is possible to prevent a synchronization shift between the video and the audio.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. The present invention is applied when a digital audio signal is recorded on a magnetic tape by a rotating magnetic head such as an 8 mm VTR. In the embodiment of the present invention, the sampling frequency is set to 48 kHz.
Then, the field frequency of the NTSC system (59.94)
Hz) is used as a reference signal.

If the field frequency is 59.94 Hz and the sampling frequency is 48 kHz, the number of samples in one field can be obtained by dividing the sampling frequency by the field frequency. That is, the number of samples in one field is 48000 / 59.94 = 800.8.

As described above, when the number of samples in one field is set so that the number of samples is the same in each field, a fraction is generated. Therefore, in one embodiment of the present invention,
A numerical value that is an integer of 2 or more close to the quotient of the above formula, for example,
And 810 are set as the number of samples.

The field recorded with the sample data number of 810 is hereinafter referred to as an E data field (Excess d).
The field recorded with the number of samples of 792 is referred to as a D data field (Diminished data).
field). Then, an identification information signal for identifying whether the number of samples in one field is 792 or 810 is simultaneously recorded.

At the time of reproduction, an identification signal extracted from the reproduced signal is detected. Then, the sampling clock formed by the PLL is frequency-divided by a variable frequency divider controlled by the identification signal, and then phase-compared with a reproduction reference signal by a phase comparator. This comparison output is supplied to a VCO after passing through a low-pass filter. Therefore, the same relationship between the recording reference signal and the sampling clock as during recording is maintained during reproduction, and the digital signal is reproduced without any problem.

First, an 8 mm VTR to which the present invention is applied
The recording format of the digital audio signal in the above will be described.

FIG. 1 shows the structure of one block of data recorded on a magnetic tape. One block is composed of 44 symbols, and a header of 4 symbols is located at the head, followed by a data section of 40 symbols. As will be described later, the header includes a block synchronization signal of one symbol, a block address of one symbol, an ID signal of one symbol, and an error detection code of the block address and the ID signal. The data section is composed of audio PCM data and C1 parity or C2 parity.

As shown in FIG.
One frame is configured by arranging 0 columns. Block addresses (0 to 44) and (65 to 10)
9) includes an audio PCM signal and a C1 parity.

Since the video signal and the time-axis-compressed audio PCM signal are recorded on the magnetic tape by one rotation head scan, the information amount of the audio PCM signal is included in one field period.

One block is composed of a header composed of a block address, an ID signal, and data, and a data block composed of only main data. An audio PCM signal is recorded in units of a two-dimensional array of symbols in which a plurality of blocks are arranged.

FIG. 2 shows an example of interleaving. As described above, one frame is composed of 110 blocks. Even-numbered sample data of the L channel and the R channel are arranged in the block addresses (0 to 44), and odd-numbered sample data of the L channel and the R channel are arranged in the block addresses (65 to 109). ing.

At the same symbol address, two blocks of data are interleaved between adjacent blocks. When looking in the same block, the upper 8 bits (Lu) and lower 8 bits (Ll) of the L channel and the upper 8 bits (Ru) and lower 8 bits (Rl) of the R channel are set to 1
It is united and interleaved for 90 sample data.

After 36 symbols of interleaved data in one block, four symbols of C1 parity are arranged. The C1 parity includes the block address, the ID, and the 3
The Reed-Solomon code RS (42, 38) is generated from 38 symbols of 6-symbol data.

The block address (45-64) is the C2
Parity is located. The C2 parity is generated from 18 pieces of data which are interleaved in the block address direction and are 5 blocks apart, and forms a Reed-Solomon code RS (22, 18). For example, with the same symbol address, the block address is 0, 5, 1
0, 15, 20, 25, 30, 35, 40, 65, 7
Four symbols of C2 parity are generated from 18 data of 0, 75, 80, 85, 90, 95, 100, 105,
The parity is the block address 45, 50, 55,
60 are arranged in four.

As described above, the number of samples in the E data field is 810, and the number of samples in the D data field is 792. Therefore, in the case of the D data field, 810−792 = 18 (sample) is not filled. . Therefore, for convenience, "0" data (00H) is arranged as dummy data.

FIG. 3 shows a configuration example of the header. As described above, the header is composed of 4 symbols, a signal for block synchronization, a block address (BA), an ID next, and a parity for the block address (BA) and ID are arranged at the beginning. I have.

When data is recorded on a magnetic tape,
The PCM data is recorded as modulated (channel coded) PCM data.
A pattern that does not apply to any channel-coded information signal is selected.

The IDs are various IDs of data to be recorded.
Information has been written. ID (E / D) indicating whether the data sample field is an E data sample field or a D data sample field
ID) is also included.

FIG. 4 shows a configuration of a recording system of a data recording apparatus to which the present invention is applied. In FIG.
An analog audio signal is supplied to the input terminal 1. This analog audio signal is supplied to the A / D conversion circuit 2. The A / D conversion circuit 2 performs band limitation by a low-pass filter and converts an input analog audio signal into a digital audio signal.

The output of the A / D conversion circuit 2 is supplied to an interleave circuit 4 and also to a sample data number discrimination circuit 5. The sample data number determination circuit 5 sets the number of samples in the field to the number of samples in the E data field (810 samples) or the number of samples in the D data field (792 samples) based on the recording reference signal FLID. Is determined. In addition,
The recording reference signal FLID is a field pulse.

The maximum address of data to be written to the interleave buffer memory 3 is determined based on the result determined by the sample data number determination circuit 5. That is, in the case of the E data field, the maximum address number is set corresponding to the sample number 810. In the case of the D data field, the maximum number of addresses is set corresponding to the number of samples 792. Then, based on the output of the sample data number determination circuit 5, the interleave address generation circuit 6
Is controlled.

Further, in the interleave buffer memory 3, C1 parity generated by the parity addition system and C1 parity
Two parities are added. At this stage, the interleaved data and parity are arranged in the interleave buffer memory 3.

Next, the data that has been time-compressed and read out by the address generated by the read address generation circuit 9 is supplied to the channel coding circuit 8.
The channel coding circuit 8 is, for example, a modulation circuit such as 8-10 modulation, which limits the run length of data so that data to be recorded can be recorded at higher density and can be easily reproduced at the time of reproduction.

The output of the channel coding circuit 8 is recorded on a magnetic tape 12 via a magnetic head 11 after passing through a recording amplifier 10. At this time, the number of samples is 79
An ID signal indicating whether the data sample field is an E data sample field or a D data sample field is generated from the sample data number discriminating circuit 5, and this ID signal (E / D ID) is recorded in the head header of each block.

FIG. 5 shows a specific configuration of the sample data number determination circuit 5. In FIG. 5, a recording reference signal FLID is supplied to an input terminal 21. This recording reference signal is a field pulse. This recording reference signal F
The LID is supplied to the J input terminal of the JK flip-flop 14.

A sampling clock is supplied to the input terminal 22. This sampling clock is supplied to the counter 15. The counter 15 has a switch circuit 2
An output of 0 is provided as a load pulse. Counter 1
5 is supplied to the E data number decoding circuit 16 and to the D data number decoding circuit 17. The output of the E data number decoding circuit 16 is supplied to a terminal 20A of the switch circuit 20. The output of the D data number decoding circuit 17 is supplied to a terminal 20B of the switch circuit 20. The output of the switch circuit 20 is supplied to the load terminal of the counter 15 and to the K input terminal of the JK flip-flop 14. At the same time, the output of the switch circuit 20 is supplied to the memory bank control counter 19. The output of the memory bank control counter 19 is output from the output terminal 23.

The switch circuit 20 is switched by the output of the JK flip-flop 14. The output of the JK flip-flop 14 is output from the output terminal 24 as an E / D ID signal for identifying whether the output is an E data field or a D data field.

The input terminal 21 is supplied with a recording reference signal FLID as shown in FIG. 6A. The rising edge detection circuit 13 detects the rising edge of the recording reference signal FILD. This edge pulse (FIG. 6B)
Is a set pulse of the JK flip-flop 14. Therefore, the JK flip-flop 14 is configured as shown in FIG.
Is set at the rising edge pulse.

The input terminal 22 is supplied with a sampling clock.
Measured at 5. Therefore, the number of sample data is obtained from the output of the counter 15. The output of the counter 15 is supplied to an E data number decoding circuit 16 and a D data number decoding circuit 17. This E data number decoding circuit 1
The decode output pulses of the 6 and D data number decode circuit 17 are supplied to the terminals 20A and 20B of the switch circuit 20, respectively.

The switch circuit 20 is switched by the output signal of the JK flip-flop 14. the first,
At time t ₀ , it is assumed that the switch circuit 20 is set to the terminal 20A side, that is, to the E data number decoding circuit 16 side. In this case, the counter 15 indicates that the number of E data is 810.
Is measured, a pulse is output from the data number decoding circuit 16. This pulse is supplied to the switch circuit 20. The output of the switch circuit 20 becomes a reset pulse of the JK flip-flop 14. Therefore, in this case,
Time T at which the number of data is measured 810 by the counter 15
_{At 1} , a pulse as shown in FIG. 8C is output through the switch circuit 20. Time T ₁ at which this pulse is output
Is temporally later than the time t ₁ of the next rising edge of the recording reference signal FLID (FIG. 6B), so that J−K
Flip-flop 14 is reset at time T _1.

Therefore, in the first field section K1, as shown in FIG. 8D, the number of samples in the E data field is set. The signal sampled and held in this section is written into the buffer memory 3 together with the E / D ID.

In the next field section K2, the counter 1
Since 5 measures 792 which is the number of data in the D data field, the switch circuit 21 needs to be on the D data number decoding side. This, J-K flip-flop 14 at time T ₁ is reset, E / D I
By using D, the switch 20 can be switched without any problem. Once T ₂ the counter 15 is 792 counts the reset pulse of the J-K flip-flop 14 is generated. Therefore, in the field section K2,
Set to the number of samples in the D data field.

Next, the switch 20 is first connected to the terminal 20B.
Suppose that it is on the D-data number decoding side. In this case, as shown in FIG.
Since it measured 2, decoding pulses from the data number the decoding circuit 17, as shown in FIG. 7C, is output at time T _01. This pulse is a reset pulse. Therefore,
Flip-flop 14 at the pulse edge of the recording reference signal FLID at time t ₀₁ is set. That is, the next field section K02 is set to the E data field.

Then, the switch 20 is connected to the terminal 20A
Side, that is, the E data number decoding side, and 810 is measured. The decode pulse from the decoder 16 is output at time _T02 . At this time _T02 , the flip-flop 14 is reset. 810 samples of the measurement pulses, since the by time t ₀₂ time output of the next set pulse earlier, the next field period K03, as well as the field period K02, needs to be as E data field.

Since the flip-flop 14 is set at the time point t ₀₂ , the field section K 03 becomes the E data field.

As described above, by using the JK flip-flop in which the rising edge of the recording reference signal is a set pulse and the number of E data or the decode pulse of the number of D data is a reset pulse, the number of sample data can be easily calculated. Can be determined.

FIG. 8 is a block diagram showing another embodiment of the present invention. In this embodiment, the data number counter and the address counter of the interleave address generating ROM 30 are shared. As described above, 8 bits are written as one symbol in the interleave buffer memory. That is, the L channel and the R channel
When considering channels, four symbols correspond to one sample data. Therefore, the E data number decoding circuit 16a and the D data number decoding circuit 17b of FIG.
May be four times the above-described decode values, respectively, and the decoder circuit 16a may decode 810 × 4 = 3240, and the decoder circuit 17a may decode 792 × 4 = 3168. The output of the ROM 30 becomes the write address of the interleave buffer memory 3.

In the above-described embodiment, the digital information signal is completed in the interleave in the field. However, in the case of the interleave in the frame, 48000 / 29.97 ≒ 1601.6. Numerical values that are two or more integers close to this quotient, for example, 1582 and 1620 are set. In this case, the recording reference signal has a frame frequency of 29.97H.
z.

When 16-bit linear quantization is performed, each word is divided into upper 8 bits and lower 8 bits, and one symbol is 8 bits. If one word is 12 bits, one symbol is 12 bits
It is said. Sampling frequency other than 48kHz,
The frequency may be 44.1 kHz or 32 kHz.

Although the case where the sampling frequency is 48 kHz has been described, the sampling frequency is 44.1 kHz and 3 kHz.
FIG. 9 shows an example of the relationship between the number of E data samples, the number of D data samples, and the sample data sequence number in the case of 2 kHz.

[0052]

According to the present invention, the number of words included in one frame of the code configuration of the digital information signal is set to an integer, and the number of words equal to the quotient obtained by dividing the sampling frequency by the field frequency on average is recorded. be able to. Thereby, even when the video frame frequency and the sampling frequency of the audio signal to be recorded are asynchronous, it is possible to prevent the occurrence of the synchronization deviation between the video and the audio.

When the external digital input is recorded in synchronization with the external clock, the frequency relationship between the sampling clock and the recording reference signal during reproduction can be made similar to that during recording. Audio PC
It is possible to prevent occurrence of excess or deficiency in the data of the M signal.

[Brief description of the drawings]

FIG. 1 is a schematic diagram used for describing a configuration in one block in a digital signal recording device to which the present invention is applied.

FIG. 2 is a schematic diagram used for explaining interleaving in a digital signal recording device to which the present invention is applied.

FIG. 3 is a schematic diagram used to explain the configuration of a header in a digital signal recording device to which the present invention is applied.

FIG. 4 is a block diagram of a recording system according to an embodiment of the present invention.

FIG. 5 is a block diagram of an example of a sample data number discriminating circuit in a block configuration of a recording system according to an embodiment of the present invention;

FIG. 6 is a timing chart for explaining the operation of one embodiment of the present invention.

FIG. 7 is a timing chart for explaining the operation of one embodiment of the present invention.

FIG. 8 is a block diagram of another example of the sample data number determination circuit in the block configuration of the recording system according to one embodiment of the present invention.

FIG. 9 is an example of a schematic diagram showing a block configuration of another embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1 analog signal input terminal 2 A / D conversion circuit 13 recording reference signal rising edge detection circuit 14 J-K flip-flop 15 sample data number measurement counter 16 E data number (810) decode circuit 17 D data number (792) decode circuit 20 Decoder circuit changeover switch

Claims (2)

(57) [Claims] 1. A number of samples data of the digital information signal in each cycle of the recording reference signal in a digital signal recording apparatus the relationship between the sampling frequency and the recording reference signal for recording digital information signals not an integer ratio, the Sampling frequency and frequency of the above recording reference signal
Close to the number of sample data calculated from the relationship with
A sample data number setting means for setting the number of sample data of a plurality of integer values have an identification signal generating means for generating an identification signal for identifying the number of sample data of the digital information signals for each cycle of upper type recording reference signal The number of sample data in the cycle of the recording reference signal,
The relationship between the sampling frequency and the frequency of the recording reference signal
Average number of sample data calculated from the
A digital signal recording apparatus so as to respond. 2. The digital signal recording device according to claim 1, wherein the number of the plurality of types of sample data is an integer close to a quotient obtained by dividing a sampling frequency by a recording reference signal frequency.