JPS62155530U - - Google Patents

Info

Publication number
JPS62155530U
JPS62155530U JP3336586U JP3336586U JPS62155530U JP S62155530 U JPS62155530 U JP S62155530U JP 3336586 U JP3336586 U JP 3336586U JP 3336586 U JP3336586 U JP 3336586U JP S62155530 U JPS62155530 U JP S62155530U
Authority
JP
Japan
Prior art keywords
counting
clock pulse
ary counter
ary
counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3336586U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3336586U priority Critical patent/JPS62155530U/ja
Publication of JPS62155530U publication Critical patent/JPS62155530U/ja
Pending legal-status Critical Current

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Landscapes

  • Transmission And Conversion Of Sensor Element Output (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本考案の基本的な回路構成を示すブ
ロツク図、および、第2図は、本考案の一実施例
による2進数―2進化10進数変換回路の構成を
示すブロツク図である。 10……プリセツタブルm進カウンタ、12…
…n進カウンタ、14……バツフア、16,18
……オアゲート、20,22,24……プリセツ
タブル・バイナリ・カウンタ、26,28……ア
ンドゲート、30,32,34……2進化10進
(BCD)カウンタ、40……バツフア。
FIG. 1 is a block diagram showing the basic circuit configuration of the present invention, and FIG. 2 is a block diagram showing the configuration of a binary number-binary coded decimal number conversion circuit according to an embodiment of the present invention. 10...Presettable m-ary counter, 12...
...n-adic counter, 14...buffer, 16, 18
...OR gate, 20,22,24...Presettable binary counter, 26,28...AND gate, 30,32,34...Binary coded decimal (BCD) counter, 40...Batsuhua.

Claims (1)

【実用新案登録請求の範囲】 符号変換されるべきm進数のデータをプリセツ
トし、所定のクロツクパルスで計数を行うプリセ
ツタブルm進カウンタと、 前記クロツクパルスで計数を行うn進カウンタ
と、 前記m進カウンタが前記プリセツトした数だけ
計数したときに前記n進カウンタの計数出力を読
み出す読出手段と、 を具備することを特徴とする符号変換回路。
[Claims for Utility Model Registration] A presettable m-ary counter that presets m-ary data to be code converted and performs counting using a predetermined clock pulse; an n-ary counter that performs counting using the clock pulse; and the m-ary counter that performs counting using the clock pulse. A code conversion circuit comprising: reading means for reading the counting output of the n-ary counter when counting by the preset number.
JP3336586U 1986-03-08 1986-03-08 Pending JPS62155530U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3336586U JPS62155530U (en) 1986-03-08 1986-03-08

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3336586U JPS62155530U (en) 1986-03-08 1986-03-08

Publications (1)

Publication Number Publication Date
JPS62155530U true JPS62155530U (en) 1987-10-02

Family

ID=30840914

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3336586U Pending JPS62155530U (en) 1986-03-08 1986-03-08

Country Status (1)

Country Link
JP (1) JPS62155530U (en)

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