JPS62154823A - Control circuit for n-m conversion circuit in data recording device - Google Patents

Abstract

PURPOSE:To generate a synchronizing (SYNC) pattern in an 8-10 conversion circuit at a prescribed period by preparing dummy data in an 8-bit data array at a part corresponding to a point of time that the SYNC pattern is to be generated, forming a means for generating a signal '1' in accordance with an address value indicating the positions of the dummy data in a buffer memory and connecting the output of the signal generating means to the SYNC/DATA terminal of the 8-10 conversion circuit. CONSTITUTION:A latch circuit 24 has eight cells corresponding to the number of bits. A shift register 26 holds 10-bit data to be an output of the 8-10 conversion circuit 10 and sends the 10-bit data to an NRZI conversion circuit as serial data. A column address line 28 and a row address line 30 from an address control circuit 22 to a memory 20 are connected to a SYNC/DATA control circuit 32 and the output of the control circuit 32 is connected to the SYNC/ DATA terminal of the circuit 10. When the column and row address lines 28, 39 indicate a memory cell to generate the SYNC pattern, the control circuit 32 generates an output '1'.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a control circuit for an nm conversion circuit in a data processing device, and more specifically, to a control circuit for generating a predetermined 5 sync pattern in the nm conversion circuit. This invention relates to a control circuit for controlling

[Prior Art] In recent years, there has been active development of systems for magnetically recording still images on still video floppy disks, playing back the images for viewing on a television monitor, or making hard copies.

There is a movement to record binary data on still video floppy disks, and a standard format for recording is currently being proposed. According to this standard format, each symbol consisting of an 8-bit data word is converted to a 10-bit codeword by an 8-10 conversion and then converted to an NRZ I code for digital recording. The correspondence relationship for 8-10 conversion has also been determined.

A 10-bit Svnc pattern has also been determined, but there is no corresponding 8-bit data word.

The recording format of this video floppy disk is a 44-symbol preamble, a 44-symbol sync frame, a 44-symbol sub-middle frame, and a 5632-symbol preamble.
Consisting of a data frame of symbols and a postamble of one symbol, each of these symbols is temporarily stored in memory to generate an error correction code prior to recording, and is then input to an 8-10 conversion circuit to generate 10 pits. converted to units. However, in the above-mentioned specified format, a 5sync pattern is to be inserted at a predetermined position.

However, as mentioned above, the 8-bit data corresponding to the 10-bit 5-sync pattern is not allocated, so at the position where this sync pattern should be generated, the 8-bit data is
Use dummy data for pit input.

A 10-bit 3 sync pattern is generated by the S VnC/Data control signal. An 8-10 conversion circuit equipped with such a Sync/-C)TTa control signal line and having a predetermined conversion function is 19
Electronic still camera held on January 22, 1985! It is disclosed in the technical documents distributed at the g-dankai technical committee.

This is shown at 10 in FIG. FIG. 5 shows the time sequence of the clock. clock /10 indicates a clock signal divided by 10, and 12 in FIG. 4 is 9
It is a PLA with human power, 10 outputs, and 25 terms, and the matrix 12A on the input side is a positive AND, and the matrix 12B on the output side is a positive OR. 1
4 is a latch circuit that latches data from the buffer memory, 26 is a shift register that serially outputs 10-bit data, and the output is NRZ T
The signal is input to an NRZl conversion circuit that converts it into a code.

This 8-10 conversion circuit 10 has S VnlO/D a
When the ta signal is "1", the 10-bit predetermined 3 ync is
Output the pattern. Also, Syno/Dat
When the a signal is “OII,” 1100 II to “FF
” (16 ways), outputs the corresponding 10-bit code.

[Problems to be Solved by the Invention] Although the 8-10 conversion circuit is known, the 5ync/σa of the 8-10 conversion circuit is
The circuit itself that sends 1'' to the ta line has not been made public.

Therefore, the present invention provides an 8-10 conversion circuit with 3 y
The purpose is to present a control circuit that generates an nc pattern.

[Means for Solving the Problem] In order to solve this problem, in the present invention, dummy data is prepared in the 8-bit data string at the portion corresponding to the point at which the 5ynC pattern should be generated, and the buffer Means for generating a signal "1P" is provided in accordance with the address value indicating the location of these dummy data in the memory, and the output of this signal generating means is used as the Sync/Dat of the 8-10 conversion circuit.
Connect to terminal a.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings illustrating an example of the present invention.

FIG. 1 shows the block causes of a data succession circuit using the present invention. Reference numeral 10 denotes an 8-10 conversion circuit for converting 8-bit data into 10-bit data, the details of which are shown in FIG. 20 is a buffer memory that temporarily stores a group of 8-bit data from a data source.

22 is an address control circuit that provides an address of the buffer memory 20 in order to read data from the buffer memory 20 constantly and at high speed.

In this memory 20, data is arranged in a matrix of memory cells as shown in FIG. ■ is the sink
frame, ■ is a sub frame, ■ to O are data frames, and @ is a postamble. Then, each of these data is sequentially read out in the numerical values and the direction of the arrow.

This situation is described in detail in a patent application filed on December 11, 1985 by the same applicant, which is an invention by the inventor of the present invention. In FIG. 2, the shaded area is the area where the 3 sync pattern should be generated, and the data in this area is dummy.

Returning to FIG. 1, 24 is a latch circuit that temporarily holds data read from the buffer memory 20 for 8-10 conversion, and includes 8 cells corresponding to the number of bits. Further, 26 is a shift register that holds the 10-pit data that is the output of the 8/10 conversion circuit 10 and sends it as serial data to the NRZ I conversion circuit. Column address lines 28 and row address lines 30 from address control circuit 22 to memory 20 are 5
ync /Data ll1II@connect to circuit 32,
The output of this control circuit 28 is the S of the 8-10 conversion circuit 10.
Connect to ync/Data terminal. This control circuit 32 is a circuit that generates a 1p output when the column address line 28 and row address line 30 point to the shaded memory cell in FIG. 2, and is a combinational logic gate. Consists of circuits.

FIG. 3 shows an example of this control circuit 32 in detail.

40.42 is an AND gate, 44.46 is a NOR gate, 48 is an OR gate, and 50.52 is an inverter.

The AND gate 40 outputs "1'° when the hatched cells in the 62nd column of FIG. Output.

The NOR gate 46 outputs lj 1 n at the time of reading the 0th column.
Output. Therefore, the OR gate 48 outputs "1'' when the hatched cells in FIG. 2 are successively displayed.

In a patent application dated December 11, 1985, the inventor of the present invention has disclosed that data to be recorded in binary on a still video floppy disk must be stored in a buffer prior to magnetic recording.
We proposed a special arrangement method at the stage of storing data in memory. This special data arrangement allows the address line 28.30 to be connected to each gate 40, 42.46.
The connection is very simple.

In the above description, an 8-10 conversion circuit has been described, but this may be any nm conversion circuit that converts n bits into m pits.

[Effects of the Invention] As can be easily understood from the above explanation, according to the present invention,
A circuit that instructs the nm conversion circuit when to generate the 3 ync pattern can be obtained with a simple circuit configuration.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a data succession circuit to which the present invention is applied, FIG. 2 is a diagram showing an example of data arrangement in a buffer memory, and FIG. 3 is a block diagram of a control circuit of the present invention. This is a detailed circuit diagram, and Figure 4 is the published 8-
FIG. 5 is a circuit diagram of a No. 10 conversion circuit, and FIG. 5 is a diagram showing the timing of the circuit shown in FIG. 10...8-10 conversion circuit 20...Buffer memory 22...Address control circuit 24...Latch circuit 26...Shift register 28.30...Address line 32-3 ynC/Q ATA control circuit patent applicant: Asahi Optical Industry Co., Ltd. TATA) Italy. Figure 1

Claims (2)

[Claims] (1) Depending on the first control signal to the control terminal, the input n
The bit signal is converted to m bits and outputted, and the second
It is equipped with an nm conversion circuit that outputs an m-bit signal of a predetermined pattern in response to a control signal of In a data recording device for recording on an external recording medium, the control terminal of the nm conversion circuit is connected to the second
An nm conversion circuit in a data recording device, comprising means for sending out a control signal, and causing the nm conversion circuit to output a predetermined pattern of m bits at a predetermined order of a series of data. control circuit. (2) A control circuit for an nm conversion circuit in a data recording device according to claim (1), wherein the nm conversion circuit is an 8-10 conversion circuit.