JPS62152164A - Manufacture of bipolar transistor - Google Patents

Abstract

PURPOSE:To reduce junction capacitance as the easy takeoff of a base electrode is kept as it is, and to obtain excellent high-frequency characteristics by growing a base layer and an emitter layer in an epitaxial manner in succession on a partially exposed collector layer again. CONSTITUTION:Collector layers 2, 3 and a base layer 4 are grown on a semi- insulating GaAs substrate 1 in an epitaxial manner in succession. An SiO2 film 11 is formed on the base layer 4. A resist mask is shaped, and one parts of the film 11 and the layer 4 are removed through etching by the mask to expose one part of the layer 3. The layer 4 may also be left thinly. A base layer 5 and emitter layers 6, 7 are grown successively on the film 11 in an epitaxial manner. One parts of the layer 4 and the layer 2 are exposed. An emitter electrode 10 is shaped onto the layer 7 and base electrodes 9 and collector electrodes 8 respectively onto the exposed layers 4 and layers 2. According to the manufacture, emitter capacitance is proportional to the junction areas of the layer 6 and the layer 5 in a re-growth section. Consequently, the junction capacitance of the section can be ignored approximately, thus acquiring excellent high-frequency characteristics.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a bipolar transistor with excellent high frequency characteristics.

Prior Art A typical structure of a conventional bipolar transistor is shown in FIG. In the figure, 13 is an n-type silicon substrate, 14 is an n-type collector provided thereon by Evita kinial growth, 15 is a p-type base provided by diffusion, 1
G is an n-type emitter provided by diffusion or alloying;
17 is a collector electrode, 18 is a base electrode, and 19 is an emitter electrode.

Although this is an npn transistor, a pnp transistor may also be used.

This example uses the same semiconductor material, silicon, to
The emitter 1 forms the base and collector.

Incidentally, the operating speed of a transistor, which is related to high frequency characteristics, depends on the transit time of electrons. In particular, the base running time is important; the shorter the base group, the faster the operating speed.

Therefore, the shorter the base group, the more desirable it is.
With such a structure, it is actually extremely difficult to reduce the base length to 1000 Å or less while maintaining good ohmic contact in terms of process.

By the way, it is known that a very high current gain can be obtained by forming a heterojunction bipolar transistor in which the emitter is formed using a semiconductor whose forbidden band energy width is larger than that of the base. This is due to the fact that, by choosing materials appropriately, the band structure of the emitter-base junction can be configured so that it does not provide much of a barrier to electrons, but provides a large barrier to holes. A typical example is
It uses AlxGa and -xAs for the emitter, and GaAs for the base and collector.

Furthermore, it is known that such a structure can significantly improve high frequency characteristics. The maximum cutoff frequency Fc of a bipolar transistor is Rb; base resistance CC; and collector capacitance. If the emitter is formed using a semiconductor having a higher forbidden band energy than the base, as described above,
By choosing materials appropriately, the band structure of the emitter-base junction can be modified to be less of a barrier to electrons.
It can be configured to provide a large barrier to holes. Therefore, the carrier degree (hole concentration) of the base can be made very high. Therefore, the base resistance can be made extremely small, and as a result, a very large maximum cutoff frequency Fc can be obtained. However, if the base length is shortened, it is difficult to take out the base electrode, and therefore it is not possible to obtain sufficiently excellent high frequency characteristics.

FIG. 7 shows a conventional example, published in Japanese Patent Publication No. 55-9830, which improves the extraction of the base electrode. In the figure, 20 is an n-type GaAs substrate, 21 is an n-type GaAs substrate forming the collector.
As, 22 is n-type GaAs forming the base, 23 is n-type Alx Ga1-XA5124 forming the emitter.
is a p-type A I
1-X As P 25 is a collector electrode, 26 is a base electrode, and 27 is an emitter electrode.

First, layers 21, 22, and 23 are formed on a GaAs substrate 20 by a liquid phase epitaxy method. Next, a part of the collector layer 21 was exposed by mesa etching, and a p-type AlxGa, -xAs layer for taking out the base electrode 24 was formed on that part again by liquid phase epitaxial method, and an electrode was formed on each. It is.

However, in such a method, traps are likely to be formed between the base layer and the base electrode extraction layer during regrowth. If the temperature during regrowth is raised, traps and traps will remain less, but interdiffusion of dopants will occur, the steepness of the junction will collapse, and the characteristics will deteriorate. Therefore, it was not possible to reduce the large resistance so much, and it was practically difficult to obtain a base group with a thickness of 1000 Å or less.

Further, in this conventional example, the area of the emitter section is larger than the area of the emitter electrode due to mask alignment.

That is, the junction area between the p-type base layer and the n-type emitter layer is larger than the emitter electrode area, and therefore the eminoterbase junction capacitance, that is, the emitter capacitance 4itCe, is larger than the electrode size δ.

By the way, the maximum frequency Ft at which the current amplification factor of the transistor is 1 is Ft= (1/2π) ・ (A-Ce+B)"
(21A, B, given by constants.

Therefore, as the emitter capacitance Ce increases, the high frequency characteristics deteriorate.

In this conventional example, if the emitter is formed on the substrate side and the collector is formed on the upper side, the collector capacitance becomes large in proportion to the area of the electrode, which is also unfavorable for high frequency characteristics as seen from equation +11.

Further, in the case of the structure of this conventional example, the area of the emitter electrode is smaller than the area of the emitter and groove due to mask alignment as described above. It is better that the area of the emitter electrode be as large as possible. This is because the contact l-resistance of the electrode is proportional to its area, and the contact resistance slows down the charging time for the transistor capacity, which also reduces the high frequency characteristics.

Problems to be Solved by the Invention As described above, with the conventional configuration, it is difficult to obtain an element with a short base length (and low resistance, small junction capacitance, and low electrode contact resistance), and it is difficult to obtain an element with a short base length (and low resistance), and a device with sufficient high frequency characteristics. You can't get what you want.

The present invention has been developed in view of these points, and while maintaining the ease of taking out the base electrode, the base length is extremely short and low, the junction capacitance is small, and the series resistance is also related to high frequency characteristics. The purpose is to provide a structure with low electrode contact resistance.

Means for Solving the Problems In order to solve the above problems, the present invention first forms a thick base electrode extraction layer having an insulating film thereon, and etches the insulating film and the number of base electrodes. After removing a portion of the exposed layer, an extremely thin base layer and an emitter layer are formed on the thinned base electrode extraction layer or the exposed collector (or emitter) layer using an epitaxial growth technique such as molecular beam epitaxy. (
By growing a semi-insulating polycrystalline film on top of the insulating film, the base length can be extremely short and low while maintaining the ease of taking out the hemi pole. This provides a structure with low capacitance and low electrode contact resistance.

Function: Due to the above-described structure of the present invention, the base length is extremely short and low, the junction capacitance is small, and the electrode contact resistance is low, so that high frequency characteristics are improved.

Example FIG. 1 shows an embodiment of the structure of the present invention.

In Fig. 1, l is a semi-insulating QaAs method plate, 2 is an n-type GaAs collector layer (electrode extraction layer), and 3 is an n-type G
aAs collector 2N, 4 is one layer of p-type GaAs base (electrode extraction layer), 5 is two layers of p-type GaAs base, 6 is n-type AlXCa, -.

As (x=0.3) 1 emitter layer, 7 is n+ type GaA
s Emitter 2 layer (electrode extraction layer), 8 is collector electrode,
9 is a base electrode, and IO is an emitter electrode.

11 is an S i O2 advance film; 5. on the top of 11; 6. 7
The shaded area is a semi-insulating polycrystalline film formed on the 5102 film.

The thickness of each layer is 40 (
1 μm, 2 n-type GaAs D collector layer 1 layer is 4000 people, 3 n type GaAsD collector 2 layer is 2000 people, 4 p
5000 p-type GaAs-based IIM, 5 p-type GaAs
400 s-base 2 layers, 6 n-type AlXGa1-xA
The number of participants is 1,500 for the first layer of the S emitter, and 1,500 for the second layer of the nf type GaAs emitter for extracting 7 H%. Each layer 2-7 was formed by molecular beam epitaxy (MBIE). The 11 3102 film had a thickness of 1000 and was formed by chemical vapor deposition.

Next, a method for manufacturing the device of this example will be described.

As shown in FIG. 2, first, each layer of 2.3.degree. 4 was formed to a predetermined thickness on a semi-insulating GaAs substrate 1 by molecular beam epitaxy. Next, by chemical vapor deposition, 5 of 11
IO2 membranes were formed on 17 of 2,000 people. Next, a resist mask is formed using normal photolithography,
With this resist mask, as shown in FIG.
Part of the 5in2 film of No. 1, p-type GaAs base of No. 4 was etched to expose a part of the collector two layers of No. 3.

In this case, the etching may be carried out to the inside of the collector layer, as shown by the dotted line in the second step, or the base layer 4 may be left thin. Etching of SiO2 film is performed using fluorine-7 acid, and etching of GaAs is performed using H2
The test was carried out using SO4-1120□-11□0 mixture. By using (OO1) as the Ga base, it was possible to form an etched portion in the shape of an inverted trapezoid as shown in FIG. 3 when viewed from the [1101 direction.

Next, the resist was removed with acetone, and SiO was removed with hydrofluoric acid.
After removing 1,000 layers of layer 2, a part of the p-type base electrode extraction layer of layer 4 was located as shown in FIG.

Next, by molecular beam epitaxy, 400 layers of p-type GaAs and 1500 layers of n-type AI were formed on top of the whole.
One layer of X Ga1-X AsI emitters and two layers of 1500 n+ type GaAs emitters were regrown as shown in FIG.

Then, by photolithography, a part of the one-color border film was removed with H2SO, -H2O2-H20 mixture &
Then, a portion of the L base 1 layer and the collector 1 layer was exposed by etching using hydronic acid.

Next, the resist part is removed with acetone, and an emitter electrode of lO is formed on the emitter 2 grown on the exposed collector layer by ordinary photolithography, vacuum evaporation, and heat treatment techniques, and an emitter electrode of lO is formed on the exposed base and collector layer. 9.8 base electrodes each. A collector electrode was formed.

The emitter capacitance Ce of the structure of this example is proportional to the junction area between the emitter and the base of the regrowth portion. In the case of this example,
This is the sum of the area of the junction epitaxially grown on the exposed collector layer and the area of the polycrystalline film junction grown on the insulating film. In this example, in order to form the p-type base of 5, B
doping of 1·10”/Cd using e and 5·10”/c using Si to form one emitter layer of 6.
M doping was performed. However, the obtained polycrystalline +
1X exhibited a high resistance of 106 ohms and was semi-insulating. Therefore, the junction capacitance in this part can be almost ignored. Therefore, the area of the eminota base junction is approximately the same as the area of the exposed collector portion, and can be minimized. Furthermore, even if the emitter electrode is made larger in area than the eminoqueous epitaxial growth area, problems such as short circuits and parasitic capacitance do not occur due to the semi-insulating nature of the polycrystalline film.

That is, it has a self-line structure of a collector, an emitter, and an emitter electrode. Therefore, the emitter electrode can be formed over the entire eminook JFT region. Since the contact resistance is proportional to the area of the junction with the electrode, this allows the emitter contact resistance to be minimized.

Reducing the series resistance speeds up the charging time for the capacitance, which greatly contributes to improving high frequency characteristics.

By using the method of this embodiment to create a car by replacing the emitter and collector, the collector capacitance can be reduced. Further, the electrode contact resistance of the collector can be reduced. The contact resistance of the electrode becomes a problem when the area is smaller, and in this case it is the collector electrode. In any case, by using the method of this embodiment, the junction capacitance and electrode contact resistance can be frozen, and the high frequency characteristics can be improved.

Furthermore, the base length of the structure of this example is extremely short, 400 people. Transit time ts of electrons in bipolar transistor
is known to be approximately expressed as follows.

, ・ ゛〔sha ``I, KA 36.) ts= (5/2)Rb -Cc' (Rb/RL
)・t b+ (3Cc+CL)RLRL; Load resistance tb; Base running time CC; Load capacity On the other hand, the base running time is t b = L b / Ve
(Given by the electron velocity in the 41Lbi base length VeH base.

In this embodiment, the characteristics of a heterojunction bipolar transistor are utilized to make the carrier concentration in the base region extremely high. (In the example, a carrier concentration of 1.lOθ/cIIl was used.) In addition, since the thickness of the portion other than the part that actually operates as the base is 5,000 thick, the base resistance related to the extraction of the base can be extremely low. Furthermore, if the manufacturing method of this embodiment is used, it is extremely easy to draw out even an extremely thin base.

Furthermore, according to this embodiment, the junction capacitance (Ce or Cc)
, base grinding resistance Rb, base length Lb, and series contact resistance can all be reduced at the same time, making it possible to obtain a transistor with excellent high frequency characteristics having an extremely high maximum cutoff frequency.

The heterojunction transistor obtained in this example exhibited the following characteristics as expected. First, we were able to form a good ohmic electrode on a very thin base made of 400 people. As a result, the base running time became shorter. Furthermore, the junction capacitance has also become smaller. Furthermore, the base resistance and electrode contact (resistance) have also been reduced to 0 or more, so when the emitter area is made the same size, the high frequency characteristics are greatly improved compared to the conventional one.

In this embodiment, an example of 400 base lengths is shown, but it is possible to make it even thinner by using molecular beam epitaxy technology. Alternatively, a similar thin base can be created using, for example, metal organic chemical vapor deposition (MO-CVD).

In this example, S r 02 was used as the insulating film, but S
Similar results have been obtained with iN, and any insulating film on which a semiconductor is not epitaxially grown may be used.

Further, in this example, GaAs-Al is used as the semiconductor.
Although x Ga + -x As is used, other semiconductor materials such as InP-1nGaAsP can also be used. Also, At: 5 degrees, X=0.3
was used, but this can be arbitrarily set to i5f in the range of 0 to 1.

In this embodiment, the emitter and collector are of n-type and the base is of p-type, but the emitter and collector may be of p-type and the base of n-type.

In this embodiment, the collector is formed on the substrate side and the emitter is formed on two parts, but as described above, it is also possible to form the emitter on the substrate side and the collector on two parts by the same manufacturing method. It is clear that in this case as well, the junction capacitance and electrode contact resistance can be reduced and the high frequency characteristics can be improved.

Effects of the Invention As described above, the present invention significantly shortens the base length and lowers the resistance while maintaining the ease of taking out the base electrode, further reduces the junction capacitance, and further reduces the contact resistance. , a bipolar transistor with excellent high frequency characteristics is provided.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a transistor formed using the bipolar transistor manufacturing method according to the present invention, FIGS. 2 to 5 are cross-sectional views of the transistor in the middle of its manufacture, and FIG. 6 is a cross-sectional view of a conventional high-bolar transistor transistor. . FIG. 7 is a cross-sectional view of a conventional heterojunction transistor. 1... Semi-insulating GaΔS substrate, 2...
・n→-GaAs collector (or emitter) 1 layer (electronic (output), 3... n-type G 3 +'
13 collector (or emitter) 2 layers, 4...
p-type Ga A S base 1 layer (electrode extraction layer), 5
....2 layers of p-type GaAs, 6...1 layer of n-type Ga 7'l S emitter (or collector),
7...N+GaAs emitter (or collector) 2 layers (electrode extraction layer), 8...Collector (
or emitter) electrode, 9...Base electrode, 1
0...Emitter (or collector) electrode, 11
...Insulating film, 12...Name of resist agent Patent attorney Toshio Nakao Haka1 person/-- Motonori, 3-- Collector Z (dh+1 Emi 9ri 2) 4- ---
~-SLC home 7 pole pick-up σ---Base 2--1 Emi 1 Hdt-tl Kore 7 127--
− Emitter? (j 7s + Kokolev 72) Figure 1
δI'/, to-・-chire 1/-, 41 to the muddy layer of Figure 2, Figure 3, Figure 4, Figure 5, Figure 6, Figure 7.

Claims (4)

[Claims] (1) After sequentially epitaxially growing a collector (or emitter) layer and a base electrode extraction layer on a semiconductor substrate and further forming an insulating film thereon, a part of the insulating film and the base electrode extraction layer are etched. It is removed to thin a part of the core base electrode extraction layer or to expose a part of the collector (or emitter) layer, on which a base layer and an emitter (or collector) layer are sequentially epitaxially grown. A semi-insulating polycrystalline film is grown on the top of the film to reduce the emitter (or collector)-base junction capacitance and to insulate the epitaxially grown emitter (or collector) from others. ), and etching a part of the semi-insulating polycrystalline film to expose a part of the base layer and the collector (or emitter) layer. ,
A method for manufacturing a bipolar transistor, characterized in that a base electrode and a collector (or emitter) electrode are formed respectively. (2) The method for manufacturing a bipolar transistor according to claim (1), wherein at least the forbidden band energy width of the emitter is larger than the forbidden band energy width of the base. (3) A method for manufacturing a bipolar transistor according to claim (1), characterized in that a III-V compound semiconductor is used. (4) The method for manufacturing a bipolar transistor according to claim (1), characterized in that silicon oxide or silicon nitride is used as the insulating film.