JPS6215157B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a timer equipped with a digital display that displays timer information such as time or time for controlling a switch or the like. Conventionally, this type of device has a plurality of timer memories for setting timer information, and an address is set for each timer memory, and when setting timer information in the timer memory, the address of the timer memory to be set is specified. There is a known system in which timer information is entered using However, with such a device, no matter what timer information is stored in the timer memory at the specified address, that timer memory is cleared and new timer information is stored, so important timer information may be cleared by mistake. I had a problem. In particular, this problem becomes more noticeable when the number of timer memories increases, as the user forgets about them. This invention was devised to solve these problems, and provides a digital display that eliminates the risk of accidentally clearing important timer information and provides excellent effects especially when the number of timer memories is large. The purpose is to provide a built-in timer. Furthermore, this invention allows the user to judge the priority of timer information by displaying this when timer information is set in all timer memories, and when setting new mode information. To provide a timer with a digital display which cannot be set without clearing a timer memory. Embodiments of the present invention will be described below with reference to the drawings. Figure 1 is a block diagram showing the circuit configuration, where 1 is a waveform shaping circuit that shapes the commercial AC power waveform input from the input terminal IN into a pulse shape, and 2 counts time based on the output of the waveform shaping circuit 1. This is a time counter. As shown in FIG. 6, this time counter 2 has a 7-word configuration of 4 bits per word, and the first word bit memories _M11 to _M13 constitute a quintal or hexadecimal counter 2a, and the second word bit memory M ₂₁ to _M24 constitute the decimal counter 2b, and the third word bit memory _M31 to _M34 constitutes 10
A hexadecimal counter 2c is constituted by the fourth word bit memories _M41 to _M43 , and a hexadecimal counter 2d is constituted.
The bit memories _M51 to _M54 of the 6th word constitute a decimal counter 2e, and the bit memory _M61 of the 6th word
~ _M63 constitutes a hexadecimal counter 2f, the 7th word bit memories _M71 to _M74 constitute a hexadecimal counter 2g, and the 6th word bit memory _M64 constitutes the morning and afternoon information setting memory 2h. ing. The signal from the waveform shaping circuit 1 is counted by a quintal or hexadecimal counter 2a in the first word. Note that the counter 2a has a power supply frequency of
At 50Hz it functions as a quinary counter, and at 60Hz it functions as a hexadecimal counter. Therefore, in the time counter 2, the decimal counter 2b in the second word counts 1/10 seconds, the decimal counter 2c in the third word counts 1 second, and the hexadecimal counter 2d in the fourth word. Count 10 seconds,
The decimal counter 2e in the 5th word counts 1 minute, the hexadecimal counter 2f in the 6th word counts 10 minutes, the decimal counter 2g in the 7th word counts 1 hour, and the 6th word counter 2f counts 10 minutes. The morning and afternoon information setting memory 2h is designed to specify morning and afternoon. 3 is a carry detection circuit that detects when there is a carry from the counter 2e that counts 1 minute of the time counter 2 to the counter 2d that counts 10 seconds; 4, 5, and 6 are 2 that are controlled objects;
Time information that controls two time switches, part 2
1st, 2nd, and 3rd timer memories for setting each timer information, including on/off control information for the two time switches, and other information that specifies whether the set time information should be repeated every day or terminated only once. , 7 is a comparison circuit that compares the time information set in each of the timer memories 4, 5, and 6 with the time information counted by the time counter 2. Each of the timer memories 4, 5, and 6 has a 4-word configuration of 4 bits per word as shown in FIG. 7, and the first word bit memories _M11 to _M14 include a memory section 4a for storing 1-minute information; 2nd word bit memory
Memory section 4 for storing 10-minute information in M ₂₁ to M ₂₃
b. A memory section 4c that stores timetable information in the third word bit memories _M31 to _M34 ; and a memory section 4d that stores on/off control information for the two time switches in the fourth word bit memories _M41 to _M43 . ,2
The word bit memory M ₂₄ is the memory section 4e that stores morning (AM) and afternoon (PM) information, and the fourth word bit memory M ₄₄ specifies whether to repeat the time information every day or finish it only once. It constitutes a memory section 4f that stores information. Each of the timer memories 4, 5, and 6 has addresses 1, 2, etc., for example.
Address number 3 is set. A comparison control circuit 8 controls the comparison circuit 7 in response to the carry detection circuit 3 detecting a carry of the time counter 2. That is, when the carry detection signal is input from the carry detection circuit 3, the comparison control circuit 8 first inputs the time information set in the first timer memory 4 and the time counter 2 to the comparison circuit 7.
The time information set in the second timer memory 5 is compared with the time information of the time counter 2, and finally the time information set in the third timer memory 6 and the time are compared. Each timer memory 4,
Addresses 5 and 6 are specified. When the time information set in the timer memories 4, 5, and 6 match the time information of the time counter 2, the comparison circuit 7 compares the time switch control information set in the corresponding timer memory with the comparison result judgment circuit. I am trying to supply it to 9. The comparison result judgment circuit 9 selects a first time switch control circuit 10 and a second time switch control circuit 11 based on the time switch control information from the comparison circuit 7.
It's like driving and controlling. Further, the comparison result judgment circuit is configured to drive and control the timer switch control circuit with priority given to the OFF information when contradictory time switch control information of ON and OFF is simultaneously input to the same time switch from the comparison circuit 7. ing. In this case, by changing the circuit configuration, it is possible to give priority to the on information, and it is also possible to determine the priority order based on the address number, or it is possible to not accept both on and off information, and to control the current control. It is also possible to maintain the state. The first and second time switch control circuits 10 and 11 are driven by the comparison result determination circuit 9 to control the first and second time switches (not shown).
Each of these can be controlled on or off. Reference numeral 12 is an input section, and this input section is used to set the device to time display mode DP and call mode as shown in Fig. 2.
CA, timer setting mode SET, time setting mode
Mode selection switch 12 for setting to CK
a, numeric keys 12b from 0 to 9, morning information setting key (AM) 12c, afternoon information setting key (PM) 12d, first time switch ON setting key (ON ₁ ) 12e, and OFF setting key key (OFF ₁ ) 12f, second time switch ON setting key (ON ₂ ) 12g and OFF setting key (OFF ₂ ) 12h, daily designation key (ED) 12i, setting key (SET) 12j, deletion Key (C) 12
A second display designation key (SEC) 12l is provided. When an input operation is performed using a switch or a key on the input section 12, the input control circuit 13 is activated, and the input control circuit 13 operates to control the address display setting circuit 14, the display mode selection circuit 15, the display setting circuit 16, the timer memory setting circuit 17, and the time counter setting circuit. The input signal is supplied to 18. 19 is a fluorescent display tube, a discharge tube, a light emitting diode,
This display 19 is a dynamic display type digital display made of a liquid crystal or the like, and as shown in FIG.
segment display elements 19c, 19d, 19
It has a 12-hour display configuration consisting of e, 19f and two colon display elements 19g, 19h that indicate the division of hour values. Each segment display element 1
9c, 19d, 19e, 19f are segment elements a, b, c, d, e, f, g as shown in FIG.
It is composed of a 7-segment display element. Further, as shown in FIG. 5, the digital display 19 has a segment display element 19f as a first digit, a segment display element 19e as a second digit, a segment display element 19d as a third digit, and a segment display element 19c as a fourth digit. , AM, and PM display elements 19a, 19b and two colon display elements 19g, 19h as the fifth digit, and each of these digits has a terminal D ₁ , D ₂ , D ₃ , D ₄ , Timing signals are input at a duty cycle of 1/6 from _D5 . In other words _{, the timing signals are D 1 ,} D ₂ , _{D 3 ,}
D ₄ , D ₅ , and D ₄ are input as one cycle, that is, the fourth digit is inputted twice in one cycle. Each of the segment display elements 19c to 19
f connects each segment element a to g to terminals A, B, C,
Commonly connected to D, E, F, and G,
And display element 19a is connected to terminal E, display element 19b is connected to terminal D, display element 19g is connected to terminal F, and display element 19
h are connected to terminal A, respectively. That is, each of the display elements 19a, 19b, 19g, and 19h displays 1 from the six segment elements a to f used to display zero among the segment elements a to g for the segment display elements 19c to 19f. The remaining four segment elements a, d, e, f except for the two segment elements b and c used in
The display element 19a is connected as a segment element e, the display element 19b as a segment element d, the display element 19g as a segment element f, and the display element 19h as a segment element a. Each terminal A
A segment drive signal having timer information for each digit is input to digits .about.G in synchronization with the timing signal to each digit. Reference numeral 20 denotes a display selection circuit provided with a display memory 21 for storing information to be displayed on the display 19. The display selection circuit 20 has, for example, a time counter on the display 19, a time counter for hours, a minute time counter for seconds, and a sub-second timer. Memory Information Information for displaying five types of information set in the address timer memory and time counter of the timer memory is stored in the display memory 21. The display memory 21 has 4 bits 1 as shown in FIG.
The memory section 21a stores 1-minute information in the bit memories _M11 to _M14 of the first word, and the bit drives _M21 to _M24 of the second word have a 6-word configuration.
Memory unit 21b for storing hourly unit information, 3rd word bit memory _M31 to _M34 , memory unit 21c for storing 1 hour unit information, 4th word bit memory
Memory section 2 that stores 10 hour information in M ₄₁ to M ₄₄
1d. Further, the memory section _51e stores the morning information in the fifth word bit memory M51, and the memory section ₂ stores the afternoon information in the bit memory M52.
1f, bit memory _M53 , colon display element 19g
A memory section 21g that stores information on the bit memory
_M54 constitutes a memory section 21h that stores information on the colon display element 19h. In addition, the sixth word bit memory _M61 is a memory section 21i for storing off information of the second time switch, and a bit memory _M62.
A memory section 21j stores the ON information of the second time switch, and a memory section 21K stores the OFF information of the first time switch in the bit memory _M63 .
The bit memory _M64 constitutes a memory section 21l that stores the ON information of the first time switch.
The display memory 21 has the above-mentioned 6-word configuration when storing display information, and the display 19
The structure is adapted to the duty cycle of 6 digits, that is, one cycle is 6 digits. Further, the display memory 21 is used when setting time information in the time counter 2, and when setting time information in the time counter 2 and each of the timer memories 4, 5,
It is also used as a temporary memory when setting timer information to 6. When the display memory 21 is used as a temporary storage device, it is shortened to a 4-word configuration as shown in FIG.
Correspondence can be established with memory sections 2e, 2f, 2g, and 2h for hour and minute information, morning and afternoon information of time counter 2, and memory sections 4a to 4f of each timer memory 4, 5, and 6. In other words, the first word bit memories _M11 to _M14 are the memory section 21a for storing 1 minute information, and the second word bit memories _M21 to
Memory section 21b, 3 for storing 10 minute information in _M23
The memory unit 21c stores timetable information in the word bit memories _M31 to _M34 , and the memory unit 21c stores information for controlling the on/off of the first and second time switches in the fourth bit memories _M41 to _M43 . Part 2
1m, the second word bit memory _M24 stores the morning and afternoon information in the memory section 21n, and the fourth word bit memory _M44 repeats the time information every day.
A memory unit 21p is configured to store information specifying whether to end the process in just one session. The display memory 21 is configured such that, for example, time value information is inputted from the first word to the fourth word by shifting to the left. 22 is an address selection circuit that determines the address of the timer memory to which timer information is to be set when setting timer information in each timer memory 4, 5, and 6; Determine whether or not timer information is set in memories 4, 5, and 6. If no information is set in the timer memories, specify the timer memory with the lowest address number among them, and all timer memories 4, 5, and 6. When timer information is set in 5 and 6, the contents are notified to the display mode selection circuit 15, display setting circuit 16, and display selection circuit 20. The display setting circuit 16 causes the display selection circuit 20 to take in the timer information input from the input section 12. Note that when the address selection circuit 22 informs that all addresses contain timer information, the timer information is prohibited from being taken into the display selection circuit 20. The address display setting circuit 14 is connected to the input section 12
When an address is designated, a display selection circuit 20 is notified to display that address and the information stored at that address on a display 19. The timer memory setting circuit 17 determines whether the timer information stored in the display memory 21 of the display selection circuit 20 from the input section 12 via the display setting circuit 16 is normal information (the set time is Must be a value from 1:00 to 12:59. Must have morning and afternoon settings. At least one timer switch on/off information must be set.) However, when it is determined that the information is normal, the timer information stored in the display memory 21 of the display selection circuit 20 is stored in the timer memory at the address specified by the address selection circuit 22. At this time, the address selection circuit 22 specifies the address of the timer memory in which timer information is to be set next, sets the display mode selection circuit 15 to the address display mode, and also sets the display mode selection circuit 15 to the display memory 21 of the display selection circuit 20.
and controls the digital display 19 to display the specified address. When determining that the information is not normal, the timer memory setting circuit 17 prohibits the timer memory from storing timer information from the display memory 21, and notifies the display mode selection circuit 15 that the information is not normal. At this time, the display mode selection circuit 15 prohibits switching of the display mode and performs control to maintain the display on the digital display 19 as it is. The determination of normality or abnormality by the timer memory setting circuit 17 is made when timer information is set in the input section 12 and the setting key 12j is operated thereafter. or,
In the timer memory setting circuit 17, when the call mode CA is set at the input section 12 and an address is specified using the numeric key 12b, the timer information stored in the timer memory at that address is called and displayed on the display 19. When the erase key 12k is operated on the input section 12 in the displayed state, the timer memory at the specified address is cleared. The time counter setting circuit 18
The time information stored in the display memory 21 of the display selection circuit 20 from the input unit 12 via the display setting circuit 16 is normal information as the time information to be set (the set time is 1:00 to 12:00). If the information is determined to be normal, the time counter 2 is displayed on the display selection circuit 20. The time information stored in the memory 21 is stored. At this time, counters 2a to 2 that simultaneously count units lower than the minimum time unit of time information, that is, 10 seconds, 1 second, 1/10 second, 1/50 second, or 1/60 second.
d is reset, and time counting is started anew according to the input frequency from this reset time. At this time, the address selection circuit 22
specifies a clock address to set the display mode selection circuit 15 to address display mode, sets an address in the display memory 21 of the display selection circuit 20, and causes the digital display 19 to display the specified address. control. When determining that the information is not normal, the time counter setting circuit 18 prohibits the time counter 2 from storing time information from the display memory 21, and notifies the display mode selection circuit 15 that the information is not normal. At this time, display mode selection circuit 1
5 prohibits switching of the display mode and performs control to maintain the display on the digital display 19 as it is. The determination of normality or abnormality by the time counter setting circuit 18 is made when time information is set in the input section 12 and the setting key 12j is operated thereafter. The display mode selection circuit 15 receives information input from the input section 12, timer information input from the timer memory setting circuit 17, time information input from the time counter setting circuit 18, and addresses input from the address selection circuit 22. The display mode to be displayed by the display 19 is determined based on the selection information, and the display mode based on the determination is transmitted to the decoder 23. At this time, especially when it is informed by the address selection circuit 22 that timer information is included in all addresses, the decoder 23 is instructed to continue the display mode that notifies this fact. The decoder 23 determines the display format of each display element of the display 19 based on the display mode determination output from the display mode selection circuit 15, and based on the determined display format, displays the display memory of the display selection circuit 20. 2
1 is displayed on the display 19. As one display format, the decoder 23 uses display memories 21 to 4 as shown in Table 1.
The bit signal is converted into seven segment drive signals, and each segment element a to g is driven by the segment drive signal. That is, for "0000" to "1001", each of the 7 segment display elements 19c, 19d, 19e, 19f is "〓"
~ "〓", "1100" becomes "〓(C)", "1101" becomes "〓(L)",
"1110" is set to "〓(U)", and "1111" is set to be "〓(F)". Note that display of "1010" and "1011" is prohibited. Further, when the display element 19c is driven in the case of "0000", zero display is not performed.

[Table] Another display format of the decoder 23 is to directly drive the four segment elements a, d, e, f with 4-bit signals without decoding the display memory 21, as shown in Table 2. It has a formality. This display format is shown in _FIG .
When energizing each digit with a duty cycle of D ₁ , D ₂ , D ₃ , D ₄ , D ₅ , D ₄ for D ₅ , it is done in the last D ₅ and D ₄ . There is.

【table】

[Table] Therefore, for example, if it is now 12:38:58.72 in the afternoon, the counter 2a will count "2" and the counter 2b will count "7" in the time counter 2, as shown in Table 3. , the counter 2c counts "8", the counter 2d counts "5",
Counter 2e counts "8" and counter 2e
f counts “3” and counter 2g counts “12”
are being counted. In this state, for example, when the mode selection switch 12a is set to the time display mode DP, the display memory 21 receives a bit signal of "8" in the memory section 21a as shown in Table 4.
The memory section 21b receives a bit signal of "3", the memory section 21c receives a bit signal of "2", and the memory section 21
A bit signal of "1" is stored in d, and a bit signal of "afternoon" is stored in the memory section 21f. Further, in the memory sections 21g and 21h, a bit signal that intermittently drives the colon display elements 19g and 19h is "1" for, for example, 0 to 4/10 seconds within one second.
It will be stored as "0" for 5/10 seconds to 1 second. The display 19 shows D ₁ , D ₂ , D ₃ , D ₄ ,
With six digits of D ₅ and D ₄ as one cycle, "8" is displayed on the segment display element 19f at first, and "3" is displayed on the segment display element 19e at the second time.
is displayed, and the third segment display element 19d
"2" is displayed on the fourth segment display element 19c, "1" is displayed on the segment display element 19c of the fourth segment, display elements 19b, 19g, and 19h are directly driven with the 4-bit signal of the sixth segment, and "1" is displayed on the segment display element 19c of the fourth segment. Although the display element 19c will be directly driven,
At this time, the bit signal is "0000", so nothing is driven. Therefore, "PM12:38" will be displayed on the display 19 as shown in FIG. Also, in this state, when the second display designation key 12l of the input section 12 is operated, "2" is stored in the memory section 21a in the display memory 21 as shown in Table 5.
A bit signal of "7" is stored in the memory section 21b, a bit signal of "8" is stored in the memory section 21c, and a bit signal of "5" is stored in the memory section 21d. Also memory part 21g
Bit signals are continuously stored in and 21h. The display 19 shows D ₁ , D ₂ , D ₃ ,
With six digits D ₄ , D ₅ , and D ₄ as one cycle, "2" is placed on the display element 19f, "7" is placed on the display element 19e, "8" is placed on the display element 19d, and "8" is placed on the display element 19c.
``5'' is displayed on each of the display elements 19g and 19h, and the display elements 19g and 19h are directly driven by the 4-bit signal. At this time, the segment display element 19c is directly driven by the 4-bit signal in the 6th position, but since the 4-bit signal is "0000", nothing is displayed. Therefore, the display 19 shows the first
As shown in Figure 1, "58:72" will be displayed. In this way, in the time display mode DP, the time is displayed in hours and minutes, and if the second display designation key 21l is operated in this state, seconds and sub-seconds will be displayed only during that time. Also, for example, turning on each timer memory 4, 5, 6,
The information storage configuration of the memory unit 4d that stores off information is configured as shown in Table 6, and for example, timer information for turning on the first time switch every day at 7:20 a.m. is stored in the first timer memory 4. If this is the case, the bit signals in the first timer memory 4 will be as shown in Table 7. In this state, when the mode selection switch 12a is set to call mode CA and the numeric key 12b is operated with "1", address 1 is specified. A bit signal indicating ``1000'' is stored, and the display 19 displays ``1000'' as shown in FIG. When the numeric key 12b is released in this state, the contents of the memory at address 1, that is, the timer information of the first timer memory 4, are stored in the display memory 21 in the form of bit signals shown in Table 9. That is, the memory section 21a receives a "0" bit signal, the memory section 21b receives a "2" bit signal, the memory section 21c receives a "7" bit signal, and so on.
The memory section 21d contains a bit signal for zero suppression, the memory section 21e contains a bit signal for "AM",
The memory sections 21g and 21h have "colon display element 1".
9g, 19h" and a bit signal "first timer switch on" are stored in the memory section 21l, respectively. Then, the display element 19f shows "0" with six digits D ₁ , D ₂ , D ₃ , D ₄ , D ₅ , D ₄ as one cycle.
"2" is displayed on the display element 19e and "7" is displayed on the display element 19d, and the segment a of the display element 19c and the segment a of the display element 19a are displayed with a 4-bit signal.
And the display elements 19g and 19h are directly driven. Therefore, "AM ^- 7:20" will be displayed on the display 19 as shown in FIG. In this case, " ^- " is set to turn on the first time switch, and ":" is set to display every day.

【table】

【table】

【table】

【table】

【table】

【table】

[Table] For example, if the second timer memory 5 stores timer information for turning off the second time switch at 9 p.m., the bit signals in the second timer memory 5 will be as shown in Table 10. Then, after operating the numeric key 12b "2" to display the 2nd address on the display 19 as "2000" and then releasing the numeric key 12b, the memory contents of the 2nd address, that is, the second The timer information in the timer memory 5 is stored in the display memory 21 in the form of bit signals shown in Table 11. That is, the memory section 21a and the memory section 21
The memory section 21c receives a "0" bit signal, the memory section 21c receives a "9" bit signal, the memory section 21d receives a zero suppression bit signal, the memory section 21f receives a "afternoon" bit signal, and the memory section 21i receives a "0" bit signal. Each bit signal of "second time switch off" will be stored. Therefore, the display device 19 has six digits as one cycle.
``0'' is displayed on f and 19e, and ``9'' is displayed on the display element 19d, and the segment e of the display element 19 and the display element 19b are directly driven by the 4-bit signal. Therefore, "PM1900" will be displayed on the display 19 as shown in FIG. In this case, "1" is set to indicate that the second time switch is off.

【table】

[Table] In this call mode CA, when the erase key 12k is operated on the input section 12, the timer memory setting circuit 1
7, the timer memory in which the timer information currently being called is stored is cleared. For example, the second timer memory 5, which is currently address 2,
The timer information is called and the digital display 19
If the erase key 12k is operated while the second timer memory 5 is being displayed, the second timer memory 5 will be cleared. Also, for example, when setting timer information in each timer memory 4, 5, 6, the mode selection switch 12
Set a to timer setting mode SET. At this time, if any of the timer memories 4, 5, and 6 has a free space, the address of that timer memory is displayed on the display 19. If two or more timer memories have free space, the one with the smallest address number is displayed. For example, for address 1, "1000", 2
"2000" for street address, "3000" for number 3
The numerical value is displayed on the display 19. Further, when timer information is stored in all of the timer memories 4, 5, and 6, bit signals as shown in Table 12 are stored in the display memory 21. That is, the memory sections 21a and 21b store an "L" bit signal, the memory section 21c stores a "U" bit signal, and the memory section 21d stores an "F" bit signal. As shown in FIG. 15, the characters "FULL" are displayed on the display 19, indicating that none of the timer memories 4, 5, and 6 is empty. Also, this timer setting mode
In SET, the timer information taken into the display memory 21 is cleared by operating the erase key 12k,
The timer information can be reset, but at this time the display on the display 19 changes to the previous address. Note that this clearing operation must be performed before operating the setting key 12j. Further, when setting time information in the time counter 2, the mode selection switch 12a is set to the time setting mode CK. By this setting, bit signals as shown in Table 13 are stored in the display memory 21. In other words, "C" is stored in the memory section 21a.
The memory section 21b stores an "O" bit signal, the memory section 21c stores an "L" bit signal, and the memory section 21d stores a "C" bit signal. However, indicator 1
As shown in FIG. 16, the characters "CLOC" are displayed at 9 to inform that the time is to be set. In this state, if you operate the numeric keys 12b to input time information, the time information will be stored in the memory section 21 of the display memory 21.
A, 21b, 21c, and 21m (FIG. 9) are sequentially taken in by shifting. Note that the "CLOC" display on the display 19 disappears. Then, when the morning or afternoon information setting keys 12c and 12d are operated and the setting key 12j is operated, the time information taken into the display memory 21 is displayed on the counters 2e and 2 of the time counter 2.
f, 2g, and 2h, and at the same time, sub-second counters 2a, 2b, 2c, and 2d are reset. Then, the counter 2a starts counting the AC power frequency. Here, the characters "CLOC" are displayed on the display 19 again, indicating that time setting is possible again. In this time setting mode CK, the display memory 2 can be cleared by operating the erase key 12k.
It becomes possible to reset the time information by clearing the time information imported into 1, but at this time as well, the display 19 will display the characters "CLOC". Note that this clearing operation must be performed before operating the setting key 12j.

【table】

[Table] The morning and afternoon information setting keys 12c, 12
d. The first time switch ON/OFF setting keys 12e, 12f and the second time switch ON/OFF setting keys 12g, 12h are used when setting information in the display memory 21. When we say that, we have a reciprocal memory structure in which we deny the other. For example, when the AM key 12c is operated, the memory section 2 of the display memory 21
1e is set to "1" and memory section 21f is set to "0". When the afternoon key 12d is operated, "1" is set in the memory section 21f of the display memory 21, and "0" is set in the memory section 21e. This relationship also applies to the on and off keys of the first and second time switches. In such a configuration, the timer memory 4,
When timer information is set for timer information 5 and 6, the mode selection switch 12a is set to the timer setting mode SET in the input section 12, and the digital display 19 displays the address of a vacant timer memory. In this state, if timer information is inputted on the input unit 12, the timer information is stored in the timer memory at the displayed address. Therefore, the user can reliably know which timer memory is available, and there is no need to specify the address of the timer memory during input operations. Therefore, unlike in the past, the user is not informed of vacant timer memories and has to rely on memory to set timer information in the timer memory. Unlike the case where the timer memory at the specified address is forcibly cleared, there is no risk of accidentally clearing important timer information. Furthermore, setting operations can be easily performed. Further, when timer information is stored in all of the timer memories 4, 5, and 6, the digital display 1
Since the character "FULL" is displayed at 9 to notify the user, the user can know that timer memories 4, 5, and 6 are all full. Therefore, the user sets the call mode to CA, checks what is stored in each timer memory 4, 5, and 6, and then compares the priorities. ，
6, the timer memory containing the lowest priority timer information may be called and cleared, and new timer information may be set. In this way, timer information can be reliably set based on the priority. Furthermore, even if the timer information is set by mistake when timer information is stored in all of the timer memories 4, 5, and 6, the timer information is prohibited from being taken into the display selection circuit 20, so the display 19 does not change the "FULL" display, allowing the user to easily notice a setting error. In the above embodiment, the digital display is used to display time information, but the present invention is not limited to this. For example, the time information can be set such as how many hours a time switch is to be turned on from a certain time. In some cases, time information can also be displayed. Incidentally, in the above embodiment, the control of two time switches has been described, but it is needless to say that the invention is not limited to this. Further, in addition to the time switch, a buzzer circuit may be provided and the buzzer circuit may be energized by the timer output, and by doing so, an alarm operation or wake-up operation can be performed. Further, in the above embodiment, a time counter that counts time based on the commercial power frequency is described, but the invention is not limited to this. It may also be something that counts the time. Further, in the embodiment described above, the time information for operating the timer is set up to the minute range, but the invention is not necessarily limited to this, and for example, time information up to the second range can be set. In this case, the comparison circuit may be configured to compare the time information of the time counter and the time information of the timer memory by detecting a carry from the sub-second range to the second range. Of course, a digital display that can display hours, minutes, and seconds will be used.

[Brief explanation of the drawing]

The figures show an embodiment of the present invention; FIG. 1 is a block diagram showing the circuit configuration, FIG. 2 is a diagram showing the input section, FIG. 3 is a diagram showing the digital display, and FIG.
The figure shows the segment configuration of a 7-segment display element, FIG. 5 shows the specific configuration of a digital display, and FIG. 6 shows the configuration of a time counter.
Figure 7 is a diagram showing the configuration of the timer memory, Figure 8 is a diagram showing the configuration of the display memory, Figure 9 is a memory configuration diagram when the display memory is used as a temporary storage, and Figure 10 is a diagram showing the configuration of the display memory. Information display diagram, Figure 11 is a display diagram of sub-second information, Figures 12 and 13 are timer information display diagrams, Figure 14 is an address display diagram, and Figure 15 is when there is no space in the timer memory. FIG. 16 is a character display diagram at the time of starting time setting. 2... Time counter, 4, 5, 6... Timer memory, 12... Input section, 17... Timer memory setting circuit, 18... Time counter setting circuit, 20...
...Display selection circuit, 21...Display memory.

Claims (1)

[Claims] 1. A timer equipped with a digital display for displaying timer information such as time or time for controlling a switch, etc., comprising a plurality of timer memories each having an address for setting the timer information; , an address selection circuit for selecting an address of a timer memory for which timer information is not set in the timer information setting state for each timer memory, and a display control for displaying the address selected by the address selection circuit on the digital display. A timer with a digital display, characterized in that it is provided with means. 2. A timer with a digital display according to claim 1, wherein the address selection circuit selects addresses in numerical order of the addresses. 3. In a timer equipped with a digital display that displays timer information such as the time or time for controlling a switch, etc., a plurality of timer memories each having an address for setting the timer information, and a If you select a timer memory address for which timer information is not set in the timer information setting state and determine that timer information is set in all timer memories, the content of the determination is output and the new timer information is updated. an address selection circuit for prohibiting the setting; and a display control means for displaying the address selected by the address selection circuit on the digital display and displaying the judgment content output from the address selection circuit on the digital display. A timer with a digital display.