JPS62151087A - Code signal detector - Google Patents

Abstract

PURPOSE:To correspond to a different kind of codes by detecting the number of logics '1' included in a data having a regulated length in which a bit polarity at a specified position is inverted corresponding to the bit pattern of a code to be detected, and performing the detection of the code to be detected. CONSTITUTION:A latch pulse is added on a latch circuit 13 through a latch pulse input terminal 14, and a pattern corresponding to a framing code is latched. With the output of the latch circuit 13, the polarity of an output from a shift register 22 is inverted at exclusive OR gate circuits 50-57, or the polarity can be held as it is. In this way, by setting the pattern of the code to be detected at the latch circuit 13, it is possible to easily correspond to the different kind of framing codes.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to a code signal detection device for detecting a framing code used in, for example, a teletext receiver.

2. Description of the Related Art As an example of the prior art, framing code detection in a teletext receiver will be described.

Teletext broadcasts include news, weather forecasts, and economic information.

This is a broadcasting system that transmits image information consisting of one character and one figure of a traffic information guide as digital data. The character signal is superimposed from the 10th horizontal scanning period (1oH) to 21H in the vertical blanking period of the television signal, and from 273H to 284H in the next field. FIG. 4 shows a schematic diagram of the character signal waveform. (a) is the horizontal synchronization signal, (
B) is a color (-ST). (C) is called a clock line (CRI), and 0 used for bit synchronization) is called a framing code (FC), and the subsequent bytes of data are Used to synchronize and rlllo
This is the bit configuration of "olol".

As an example of the conventional 7-lemming code detection circuit, the fifth
A circuit as shown in the figure is known. In the figure, a character signal is input to the character signal input terminal 20, and a clock signal for sampling two character signals is input to the clock signal input terminal 2.
1 is added to the shift register 22 via 0. This shift register 22 converts the serially transmitted character signal into parallel data and outputs it. The not gate circuits 23 to 25 are used to invert the logic "0" portion of the framing code and convert it to logic "1". In this way, the framing code is transferred to shift register 2.
2, all the inputs of the AND gate circuit 26 become logic "1" due to the NOT gate circuits 23 to 26, and the framing code detection signal is output to the AND gate circuit 26 via the framing code detection signal output terminal 27.
is output from.

There is a known circuit as shown in FIG. 6 that allows the framing code to be detected even if one bit in the framing code is erroneous.

In this figure, the same parts as in FIG. 5 are given the same numbers. 28 to 36 are NOT gate circuits, 36 to 43 are AND gate circuits, and 44 are OR gate circuits. When the framing code has a 1-bit error, the shift register 22
, a framing code detection signal is output from any one of the AND gate circuits 36 to 43.In addition to the above example, as shown in FIG. A method is also being considered in which a 1-bit error code is used as an address and a ROM is used in which specific data is stored in advance for that address (Japanese Patent Laid-Open No. 59-284).

Problems to be Solved by the Invention However, in a circuit like the one shown in FIG. 6, correcting one via FS increases the size of the circuit configuration and increases the possibility of failures due to incorrect wiring. Furthermore, in the circuit shown in FIG. 7, the efficiency of the ROM used is poor.

The present invention has been made in view of these points, and it is an object of the present invention to provide a code signal detection device capable of detecting up to one pit error υ with a small number of parts.

Means for Solving the Problems In order to achieve the above objects, the present invention provides a serial-to-parallel conversion circuit that converts serial data into parallel data, and a polarity inverter that inverts the focus polarity of a specific position of the data converted into parallel data. The focus of this specific position is comprised of a Wallace tree element that detects the number of logic "1"s from parallel data whose polarity has been inverted. Correspondingly, the code to be detected is detected by detecting the number of logic "1"s included in a certain length of data with bit polarity inverted at a specific position.

EXAMPLES Hereinafter, the present invention will be explained in detail using FIGS. 1 to 3.

FIG. 1 is a circuit block diagram showing the configuration of a code signal detection device according to an embodiment of the present invention when used in a framing code detection circuit in a teletext receiver. In the same figure,
1 is a 7-person Kaworth tree element (for example, TI's SN
NA3, LS276), 2 to 6 are not gate circuits,
7 is a NOR gate circuit, 2o is a character signal input terminal, and 21 is a clock signal input code detection signal output terminal.
Figure 6.

It is similar to that in FIG. FIG. 2 is a functional block diagram of a Wallace tree element with a 7-bit slice input. Numerals 8 to 12 in the figure are full adders, and as is clear from the 0 table showing the logic table of full adders, the bit slice input and carry input in Figure 2 are all logic "o". If so, all outputs are logic ro4. Also, B11. If one bit slice λ force -y'r-P ≠ 1 is logic "1" and all other bit slice inputs and carry inputs are logic "○", all outputs other than 2n are logic "○". "become. Furthermore, all bit slice inputs are logic "0", one of them is logic "0" and the other is logic "1".
However, all outputs except 2n are logic "0"
become. Therefore, in Fig. 1, 7 bits out of 8 shift register output pits are connected to the bit slice input of the Wallace tree element, the other 1 pit is connected to the carry power of one of the Wallace tree elements, and the carry power of the other is connected to the bit slice input of the Wallace tree element. If grounded, +2 n+1 n+
1 The framing code can be detected by using the OR output of the three outputs of the Oles tree element outputs 2", 2, and C2. Note that 1A and 1B.

1C to sA, sB, and sC are input terminals, and 1CA to 5cA and 1Σ to 5Σ are output terminals.

Next, FIG. 3 shows another embodiment of the present invention. Compared to FIG. 1, instead of the NOT gate circuits 2 to 6 in FIG. 1, a latch circuit 13 and exclusive OR gate circuits 50 to 6 are used.
Connect 7 as shown in Figure 3. A latch pulse is applied to the latch circuit 13 via the launch pulse input terminal 14, and the pattern corresponding to the framing code is latched. The output of the launch circuit 13 allows the exclusive OR gate circuits 50 to 67 to invert the polarity of the output from the shift register 22 or maintain the same polarity. For example, if "111o0101" is set for D4 to D7 of the latch circuit 13, the framing code can be extracted in the same way as in FIG. By setting the code pattern to be detected in the latch circuit 13 in this way, it becomes possible to easily handle different framing codes.

Effects of the Invention According to the present invention, it is possible to detect a code to be detected with a simple circuit configuration. Furthermore, even if the pattern of the code to be detected changes, it is possible to handle different codes by changing the value set in the latch circuit.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram of a code signal detection device according to an embodiment of the present invention, FIG. 2 is a functional block diagram of a 7-pit caucasian tree element, and FIG. 3 is a circuit block diagram of another embodiment of the present invention. 4 are waveform diagrams showing a schematic structure of character signals, and FIGS. 5 to 7 are block diagrams of conventional framing code detection circuits. 1...7 people Kawores tree element, 2-6.
...Not gate circuit, 7...Nor gate circuit, 8-12...Full adder, 13...
...Latch circuit, 22...Shift register, 6
0 to 57...Exclusive OR gate circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 3
figure

Claims (1)

[Claims] a serial-to-parallel conversion circuit for converting serial data including a detected code signal into parallel data; a polarity inverter for inverting the polarity of bits at fixed positions of the output of the serial-to-parallel conversion circuit; 1. A code signal detection device comprising: a Wallace tree element for detecting a number of ``1''.