JPS62149225A - Fsk demodulator - Google Patents

Abstract

PURPOSE:To attain a processing circuit without needing an analog circuit by providing a D flip-flop inputting an output signal being the result of exclusive OR by a phase comparator as information and using an output of a frequency divider as a clock pulse. CONSTITUTION:An output C being the result of exclusive OR of phase difference between an input signal A and a signal B fed back by a PLL circuit by using a phase comparator 1 enters a data input terminal of a D FF 8. On the other hand, a clock pulse signal D being the multiplication resulting from the fundamental wave being the same frequency as that of a phase consecutive FSK modulation signal frequency-divided by a frequency divider 7 of the PLL circuit enters the clock input terminal of the D FF 8. The D FF 8 reads the information given to the data input terminal by using the clock pulse signal and stores it until at least the next clock pulse signal is given as its capability, then the output E of the D FF 8 displays the state of the signal C from the comparator 1 at the leading of the clock pulse signal D.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides
This relates to the S Ktll device.

[Prior Art] FIG. 4 is a block diagram showing a conventional FSKtl adjustment device.

In the figure, (1) is a phase continuous FSK modulation signal and a PLL
The phase comparator (2) detects the phase difference with the feedback signal of the frequency divider (7) constituting the circuit;
), (3) is a waveform shaping circuit that shapes the waveform of the signal that has passed through low-pass filter (2) and outputs it as a demodulated output, and (4) is a phase comparator. The output signal from (1) generates an oscillator (
5) or a frequency switching circuit for switching the oscillator (6), (5)
) is an oscillator with a frequency corresponding to the frequency (f1) for "H" (high level or mark signal) of the phase continuous FSK modulation signal, and (6) is for the "low level or space signal" of the phase continuous FSK modulation signal. An oscillator with a frequency corresponding to the frequency (f1), (7) is a frequency switching circuit (4)
In order to smooth the sudden change in the discontinuous signal that occurs when switching from , is a frequency divider that constitutes a feedback loop of a PLL circuit. In addition, a phase comparator (1), a frequency switching circuit (4), an oscillator (5), an oscillator (6)
, frequency divider (7) constitute a known PLL circuit.

The conventional FSK demodulator is configured as described above, and utilizes the phase difference between the phase continuous FSK modulation signal that is the input signal and the feedback signal of the PLL circuit, and uses the oscillator (5) of the "H" frequency and the "L" frequency oscillator (5). Adjust the ratio of switching between the two frequencies of the oscillator (6) with a frequency for was used to convert it into a demodulated signal.

The output signal of the phase comparator (1) includes phase continuous FSK.
Since it also contains a carrier wave component that carries the modulated signal, it is necessary to use a low-pass filter (2) to remove the high frequency component that is the carrier wave component, and then convert it into a demodulated signal using a waveform shaping circuit (3). There wasn't.

[Problems to be Solved by the Invention] The circuit configuration of the conventional FSK demodulator as described above also includes analog circuits such as the low-pass filter (2) and the waveform shaping circuit (3), so the overall circuit configuration is Adjustment was complicated and required fine adjustment. Furthermore, since the characteristics may change depending on usage conditions such as the ambient temperature, high accuracy cannot be expected, and there remain concerns about reliability and reliability.

Therefore, this invention was made to solve these problems, and the circuit configuration of the FSK 1ml device can be configured with a small number of electronic components, and it is easy to adjust.
Moreover, it is an object of the present invention to obtain an FSK demodulator having high accuracy.

[Means for Solving the Problems] The FSK demodulation device according to the present invention includes a phase continuous FSK modulation signal in which frequencies (f1) and (f1) are transmitted as a modulation signal H'' or II L II; H
The feedback signal of a PLL circuit consisting of a frequency switching circuit and a frequency divider, which is equipped with an oscillator for II and an oscillator for "L", is made into an output signal by exclusive ORing with a phase comparator, and this output signal is used as a D This circuit has a circuit configuration that converts it into a digital signal using a type flip-flop and outputs it as a demodulated signal.

Effect] In the present invention, the FSK demodulator includes a D-type flip 7.
The phase state is determined using the 0-tube, and the entire circuit can be configured as a pulse signal processing circuit without requiring analog circuits such as a low-pass filter and a waveform shaping circuit.

[Embodiment] Fig. 1 is a block diagram of an FSK demodulator showing an embodiment of the present invention, and Fig. 2 shows an input signal 11 HI to the circuit shown in Fig. 1.
Figure 3 is a timing diagram when a phase-continuous FSK modulation signal with a frequency corresponding to I is input. It is a timing chart diagram when inputting.

In the figure, (1), (4) to (7) are the same or equivalent components of the conventional example.

(8) is a D type for outputting a demodulated signal by inputting the output signal from the phase comparator (1) to the data input terminal and the clock pulse signal from the frequency divider (7) to the clock input terminal. It's a flip flop.

The operation of the FSK demodulator configured as described above will be explained using timing charts shown in FIGS. 2 and 3. Note that (A) is a phase continuous FSK input signal.
Modulation signal, (B) is the signal fed back by the PLL circuit, (C) is the output signal from the phase comparator (1), (D
) shows the clock pulse signal from the frequency divider (7), and (E) shows the demodulated output signal from the D-type Noritub flop (8).

For example, if the high frequency (f1) of the phase continuous FSK modulation signal is a digital signal "H" and the low frequency (T2) is a digital signal "no", the frequency of the phase difference (Δt) with the feedback signal of the 811 circuit (f1) or (T
The ratio to the period (T1) or (T2) corresponding to 2) is larger in the case of "H" than in the case of "L".

In other words, there is a relationship between the period (T) and the frequency (f) of T=1/f, and as the frequency (f) increases, the period (T) decreases, so the high frequency (f1) and the low frequency ( T2)
In addition, if the phase difference (Δt) is the same, the ratio of the phase difference to the period Δt/T is Δt/T1 > Δt /T2, and the higher frequency (f1) is lower than the lower frequency (T2).
This means that it will be larger than in the case of . This can be understood by comparing (A) and (B) in FIGS. 2 and 3, respectively.

The phase difference between the signals (A) and (B) is exclusive ORed using the phase comparator (1), and the output (C) is input to the data input terminal of the D-type flip-flop (8). .

On the other hand, the frequency is divided by the frequency divider (7) of the PLL circuit and the phase continuous F
The clock pulse signal ([), which is the result of multiplying the fundamental wave having the same frequency as the SKI signal (the figure shows double multiplication), enters the clock input terminal of the D-type flip-flop (8). .

The D-type flip-flop (8) has the ability to read the information given to the data input terminal when a clock pulse signal is given and store it at least until the next clock pulse signal is given. The output of the D-type flip-flop (8) is as shown in the demodulated output (E). There is.

In other words, in the case of Fig. 2, since the signal (C) at the rising edge of the clock pulse signal (D) is "H", the vll output output E) indicates "H", and in the case of Fig. 3, the opposite is true. Since the signal @(C) at the rising edge of the clock pulse signal (D) is "L", the demodulated output (E) also indicates L".

As explained above, the FSKtl:l device of the present invention does not require the conventionally required low-pass filter (2) or waveform shaping circuit (3), and the phase continuous FS of the input signal is
The K modulated signal can be easily converted into a demodulated digital signal.

Next, the PLL circuit of this FSK demodulator has the frequency (f1) and (T2) of the phase continuous FSK modulation signal of the input signal.
), a frequency switching circuit (4) comprising an oscillator (5) and an oscillator (6) with frequencies higher than the frequencies (f1) and (T2), respectively, may be used, but these may be replaced by phase continuous FSK. A phase comparator (1) converts the ratio of the phase difference between the modulation signal and the feedback signal of the PLL circuit into a voltage signal.
A voltage controlled oscillator called a VCO which oscillates in response to this signal may be used. Generally, this type of voltage controlled oscillator is often used in a PLL circuit, and in this case, the number of oscillators can be reduced to one.

Therefore, it is possible to promote the simplification of the circuit, so that the number of electronic components can be reduced, and the circuit configuration can be made entirely of digital circuits.

[Effects of the Invention] As explained above, the present invention uses a phase-continuous FSK modulated signal and a feedback signal of a PLL circuit as an input signal, which is an exclusive OR of the phase difference between a phase continuous FSK modulation signal and a feedback signal of a PLL circuit. Since it is an FSK demodulator that converts into a digital signal using a flip 70 tube and obtains a demodulated output, it does not require analog circuits such as a low-pass filter and waveform shaping circuit, making it easy to adjust and adapt to usage conditions such as changes in ambient temperature. Since the characteristics do not easily change due to changes in , highly accurate demodulation can be performed. Furthermore, the number of electronic components can be reduced, resulting in an inexpensive and space-saving device.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an FSK demodulator showing an embodiment of the present invention, and FIG. 2 is a timing chart when a phase-continuous FSK modulation signal with a frequency corresponding to the input signal "HTT" is input to the circuit of FIG. 1. Figure 3 is a timing chart when a phase continuous FSK modulation signal with a frequency corresponding to the input signal "L" is input to the circuit in Figure 1, and Figure 4 is a block diagram showing a conventional FSK demodulator. be. In the figure, (1)...phase comparator, (2)...low-pass filter, (3)...waveform shaping circuit, (4)...frequency switching circuit, (5)...frequency f1 oscillator with frequency f2, (6)... oscillator with frequency f2, (7)... frequency divider, (8)... D-type flip-flop. In addition, in the figures, the same reference numerals and the same symbols indicate the same or equivalent parts.

Claims (2)

[Claims] (1) Frequencies (f1) and (f2) are set to “H” of the pulse signal.
a phase-continuous FSK modulated signal transmitted as "" or "L", a frequency switching circuit comprising an oscillator corresponding to the "H" signal and an oscillator corresponding to the "L" signal, and dividing the output of the frequency switching circuit. a PLL circuit comprising a frequency divider that performs a phase change, a phase comparator that compares the phase of the output of the frequency divider with the phase continuous FSK modulation signal, and an output signal obtained by exclusive ORing by the phase comparator as an information input, An FSK demodulator comprising a D-type flip-flop that uses the output of a frequency divider as a clock pulse signal. (2) Claim 1, characterized in that the frequency switching circuit comprising an oscillator corresponding to the "H" signal and an oscillator corresponding to the "L" signal of the PLL circuit is a voltage controlled oscillator. FSK demodulator.