JPS62149098U - - Google Patents
Info
- Publication number
- JPS62149098U JPS62149098U JP3462086U JP3462086U JPS62149098U JP S62149098 U JPS62149098 U JP S62149098U JP 3462086 U JP3462086 U JP 3462086U JP 3462086 U JP3462086 U JP 3462086U JP S62149098 U JPS62149098 U JP S62149098U
- Authority
- JP
- Japan
- Prior art keywords
- buzzer
- clock
- sound
- period
- control circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010355 oscillation Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Description
第１図は本考案のブザー制御回路に係る一実施
例を示す回路図、第２図及び第３図は第１図に示
す実施例の動作を説明する図、第４図は従来のブ
ザー制御回路を示す回路図、第５図及び第６図は
第４図に示す回路の動作を説明する図である。
１０…ＣＰＵ、１１…制御回路、１２…カウン
タ、１３，１５…発振器、１６…出力回路。
Fig. 1 is a circuit diagram showing one embodiment of the buzzer control circuit of the present invention, Figs. 2 and 3 are diagrams explaining the operation of the embodiment shown in Fig. 1, and Fig. 4 is a conventional buzzer control circuit. The circuit diagrams shown in FIGS. 5 and 6 are diagrams for explaining the operation of the circuit shown in FIG. 4. 10... CPU, 11... Control circuit, 12... Counter, 13, 15... Oscillator, 16... Output circuit.
Claims (1)
クをゲート手段がブザー鳴音期間にのみ通過させ
てブザー鳴音パルスとしてブザーに出力するブザ
ー制御回路において、 前記ブザーを連続して鳴音させる連打の回数が
設定される連打回数設定手段と、 前記鳴音期間及び鳴音と鳴音の間の休止期間が
１周期の極性で示されるブザークロツクを発生す
るブザークロツク発生手段と、 このブザークロツクを前記連打回数に応じた数
だけ通過させて、前記ゲート手段に出力するブザ
ークロツク制御手段とを具備したことを特徴とす
るブザー制御回路。[Scope of Claim for Utility Model Registration] A buzzer control circuit in which a gate means allows a clock for buzzer sound outputted from an oscillation means to pass only during a buzzer sounding period and outputs the clock as a buzzer sounding pulse to a buzzer, comprising: a number-of-beats setting means for setting the number of consecutive hits to make the sound sound; and a buzzer clock generating means for generating a buzzer clock in which the sound period and the rest period between the sounds are represented by the polarity of one cycle. . A buzzer control circuit comprising: a buzzer clock control means for passing the buzzer clock a number of times corresponding to the number of consecutive hits and outputting the result to the gate means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3462086U JPS62149098U (en) | 1986-03-12 | 1986-03-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3462086U JPS62149098U (en) | 1986-03-12 | 1986-03-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62149098U true JPS62149098U (en) | 1987-09-21 |
Family
ID=30843348
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3462086U Pending JPS62149098U (en) | 1986-03-12 | 1986-03-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62149098U (en) |
-
1986
- 1986-03-12 JP JP3462086U patent/JPS62149098U/ja active Pending
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