JPS62148993A - Display controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a rusk scan type display device (
The present invention relates to a display control device using a display device (display device).

This invention includes a period rl during which information corresponding to a display screen can be written to a refresh memory, a CPU (
microprocessor) so that it can be easily detected.

Hereinafter, the present invention will be specifically explained with reference to Examples.

FIG. 1 is a block diagram of a CRT display device showing one embodiment of the present invention.

The outline of the CRT display device in this embodiment is as follows.

Information to be displayed is written to the refresh memory (5) by an input source such as the CPU (11) via the bus driver (2).This information includes address information indicating the display position on the CRT screen, ASCII (ASCI I)
) code and other character display codes. The above address information is sent to the address decoder (11) and the address selector (
4) and is input to the refresh memory (5).

The refresh memory (5) has addresses corresponding to character display addresses assigned on the CRT screen. Therefore, the refresh memory (5) is
It has a memory capacity that can store code information for the total number of characters that can be displayed on a CRT screen.

For example, if the number of characters is 32 characters horizontally and 16 lines vertically, a storage capacity of 32×16 bytes is required per screen. In this embodiment, the refresh memory (5) comprises two
There is one that has a storage capacity of 0.048 bytes and can store data for four screens. Therefore, the address information has an 11-bit configuration.

Generally speaking, the address information in a microcomputer system has a 16-bit configuration, so the address information of the CPU, etc. is converted into an 11-bit refresh memory address, and an address signal that specifies the readout circuit a2, which will be described later, is formed. This is done by the ship's address decoder commander.

The address selector (4) receives address information from the CRT controller (3), which will be described later, and the CPU (1).
This is for switching address information from input sources such as .

Reading of the refresh memory (5) is performed character by character sequentially, using the timing pulse (MA) corresponding to the character address of the CRT formed by the CRT controller (3) as 7) "response information. The output code information is converted by a pattern generation circuit (6) into a pattern signal in which each character is composed of dots.

This pattern generation circuit (6) is constituted by a read-only memory (ROM) in which pixels such as characters are written. 1 - Therefore, the character code to be displayed is given from the refresh memory (5) to the pattern generation circuit (6), that is, the character address of the pattern generation circuit (6) is specified, and the raster address is specified. As a result, the output becomes a character pattern signal synchronized with the raster scan timing.

This pattern output is output from the parallel/serial conversion circuit (7
) is converted into a serial video signal.

This serial video signal is synthesized by a video control circuit (8) with a synchronization pulse (5YNC) and a display timing pulse (DISPTMG) forming an effective display screen to display characters on the CRT screen.

The timing controller (9) has a built-in oscillation circuit,
A character lock (CLK) is the basis of the address timing pulse (MA) of the refresh memory (5) and a raster address timing pulse (RA) of the pattern generation circuit (6), and a video clock is used to obtain serial pixel data. (■CLK) etc.

The CRT controller (3) has a horizontal display character register,
various control registers such as a vertical display character register; a refresh memory (5); in other words, a 9-line character counter that specifies an address in synchronization with the raster on the CRT screen;
Addressing (MA) of the refresh memory (5), which is composed of a CRT horizontal and vertical synchronization signal generation circuit, a raster control circuit, a cursor control circuit, etc., and is synchronized with the CRT raster.

The raster designation (RA) of the pattern generation circuit (6) is performed to form pixel data as described above, and C
It forms RT synchronization pulses, etc.

As this CRT controller (3), for example, a monolithic integrated circuit with the trade name HD46505J can be used.

Note that αυ is a timing pulse generation circuit that forms an access timing signal from an input source to the resource memory (5), and the display timing pulse (DIS)
PTMG) is input and the vertical blanking period is extracted to form a -F timing pulse (STATUS). Ht-z is a readout circuit that reads out this output.

In the above-mentioned CRT display device, for example, as shown in FIG. 3, the number of rasters constituting the CRT display screen section (131) in non-interlaced mode is 240, and 10% of the screen is displayed on the top, bottom, left and right sides. A border part (the part marked with a line) is provided to constitute the effective display screen a.This border part is
This is necessary to prevent displayed characters from being displayed off the screen due to variations in horizontal and vertical driving ability.

In a CRT such as a home television receiver, the horizontal scanning time (H) is about 63.5M5 (milliseconds).

If the blanking time (t4) is 9.3 MS, the horizontal scanning time to form the display screen 0□□□ is 54.2 MS. Therefore, if a border section of 10% (1,,1,) is provided on the left and right sides, as in ``Double Series'', ? ++j2 is 5,4 M S, and the scanning time (t,) to form the effective display screen Q4) is 4
It becomes 3.36M5.

Therefore, the CRT controller (3) calculates the above effective display time (t3) per horizontal scanning time (II) to nl+
Display timing (DISPT) with + and other border times and blanking times (blanking time)
MG).

On the other hand, in the vertical direction, since the number of rasters on the display screen a is 240, and the upper and lower borg portions are provided at Vr10% (tIl, t,), t.

t is 24 raster lines (24X63.5MS)
The number of rasters forming the effective display screen α is 192, and the time (t,) is 192×6.
It becomes 3.5MS.

Therefore, for one display screen (V), a display timing (DISPTMG) is formed in which the effective display time (t,) is set to "1" and the others are set to "o" (blanking).

This display timing pulse (DISPTMG) is formed as shown in FIG. As shown in the figure, this timing pulse (DISPTMG) is
When configured in non-interlace mode using a CRT of this type, one display screen (V) is 1/60 seconds, which includes 192 horizontal display timing pulses (H) and this horizontal display timing pulse (■( ) becomes a pulse signal having a duty blanking part corresponding to 70 parts.

In the NTSC system, the vertical blanking section is
Since the number of rasters is 525 and the number of rasters in non-interlace mode is 52572, 262.5-
The horizontal display timing corresponds to 192-1-70 pieces. Of these, 48 times correspond to the above time (ta+ta), and 22 times correspond to the vertical retrace time (tS) VC.

In this embodiment, the border timing for forming the effective display screen α and the blanking timing consisting of the blanking timing are used to control the input source such as the CPU when changing the display contents of the CRT. The purpose is to allocate the access timing of That is, during the blanking period, the CRT display device stops reading the refresh memory, in other words, stops the operation for displaying characters, so the CRT display device can refresh the display screen without flashing a part of the display screen.
The contents of memory can be changed.

In this case, as is clear from the above, the horizontal blanking period is as short as 20M5, and even if this is an accessible time period, no substantial write operation from an input source such as the CPU can be expected.

Therefore, in order to prevent the CPU from performing unnecessary operations, this horizontal blanking period is deleted and only the vertical blanking period (4, 4M5) is used as the access timing.

FIG. 2 is a circuit diagram showing an embodiment of a circuit that erases this horizontal blanking period and forms the access timing signal.

This circuit uses the display timing signal (DISP TM
An inverter (IN) that forms an inverted signal of G), a one-shot multivibrator (O8,) that forms an output pulse of 110# level at the rising timing of this inverter output, and @ at the rising timing of this output
It is composed of a one-shot multivibrator (O8,) that forms an output pulse of OII level.

The one-shot multivibrator (081) at the front stage is a one-shot multivibrator of the IJ) regregable type for erasing horizontal blanking, and has a time constant circuit (R1) that determines the output pulse width.

The value of C1) is set to be longer than the horizontal scanning time (H). This time constant (R1, Cr) causes the output pulse to be “1”.
Since the output pulses are activated one after another before changing to the ``level,'' an output pulse (O8,) with horizontal blanking removed is obtained as shown in FIG.

The multivibrator (O8,) at the latter stage is for forming the above-mentioned access timing circuit (8TATUS), and the time constant circuit (rtt, C*) K'l, 4
A 10'' level pulse (OSt) on the order of MS is formed.

Since the one-shot multivibrator (OSt) described above includes the first display period, the one-shot multivibrator (OSt) is provided to form a true vertical blanking pulse.

These timing signals (STA, TUS) are used as switching signals for the address selector (4) as shown in FIG. 1, and are also output to the data bus (DATA) via the readout circuit (2). It is something to do. As a result, the CPU, etc.
When changing the contents, (1) First, address α20 of the reading circuit is specified, the signal (STATUS) is read out, and it is determined whether or not writing is possible. ■Writable (“0”
), send the address information and data of the refresh memo January 5) to perform the memorization. ■After writing, specify the readout circuit a again to determine whether reading is possible or not, and the signal (STATUS) is set to “O”.
At this time, it is confirmed that the above writing operation has been completed completely, and the series of writing operations is completed.

The above confirmation operation (■) is performed during the blanking period when determining before writing, but when performing the filling operation, it is during the display period and the oath may not be performed. This confirmation operation is performed.

If a display device is used for programming Divanoku, etc., if there is a writing error like the one mentioned above, it can be identified by a single display, but if there is a mistake like the one mentioned above while executing a program in a video game, etc., the game will be affected. The contents will not follow the program, resulting in malfunction.
This can be prevented by performing the above simple confirmation operation.

The present invention is not limited to the embodiments described above, and the means for erasing horizontal blanking can be modified in various ways, and the horizontal and vertical pulses can be modified depending on the display character configuration.

INDUSTRIAL APPLICABILITY The present invention can be widely used in CRT display devices using the Rusk scan method.

[Brief explanation of drawings]

IEI diagram is a block diagram of a CRT display device showing one embodiment of the present invention, FIG. 2 is a circuit diagram showing one embodiment of the timing pulse generation circuit in FIG. 1, and FIG. FIG. 4, which is a diagram for explaining the configuration and timing of the display screen showing the embodiment, is an operation waveform diagram of the circuit shown in FIG. 2. (1)...C'PU, (2)...Bus driver, (
3)...CRT controller, (4)...address selector, (5)...refresh memory, (6)
...Pattern generation circuit, (7)...Parallel/serial conversion circuit, (8)...Video control circuit, (9)...Tinging controller 5, (10)--
・Address decoder, (11)...timing pulse generation circuit, (12)...reading circuit, (13)...
-Display screen, (14)...Effective display screen.

Claims (1)

[Claims] 1. a microprocessor, a bus line coupled to said microprocessor, a refresh memory in which information to be displayed on a display device is stored, and a transfer of information during vertical blanking periods to said refresh memory via said bus line; synchronization for a flip-flop having a control signal applied thereto signifying permission for writing and made accessible by the microprocessor via the bus line, and a display control signal being applied via the bus line for the display device; A display control device comprising: a display control circuit for forming a signal, an address signal for the refresh memory, and a control signal for the flip-flop.