JPS6214859U - - Google Patents
Info
- Publication number
- JPS6214859U JPS6214859U JP10718485U JP10718485U JPS6214859U JP S6214859 U JPS6214859 U JP S6214859U JP 10718485 U JP10718485 U JP 10718485U JP 10718485 U JP10718485 U JP 10718485U JP S6214859 U JPS6214859 U JP S6214859U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- buffer
- inverting amplification
- television signal
- inverting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 6
- 230000000903 blocking effect Effects 0.000 claims description 4
- 230000003321 amplification Effects 0.000 claims 5
- 238000003199 nucleic acid amplification method Methods 0.000 claims 5
- 238000010586 diagram Methods 0.000 description 9
- 230000001360 synchronised effect Effects 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Landscapes
- Picture Signal Circuits (AREA)
- Synchronizing For Television (AREA)
Description
第１図ないし第３図は本考案の実施例を示し、
第１図は本考案の実施例の回路図、第２図はゴー
スト成分が弱い場合の各部信号波形図、第３図は
ゴースト成分が強い場合の各部信号波形図である
。第４図は同期信号処理回路図である。第５図な
いし第９図は従来例を示し、第５図は従来例の回
路図、第６図はゴースト成分がない場合の各部信
号波形図、第７図はゴースト成分がある場合の各
部信号波形図、第８図はゴースト成分が弱い場合
の信号波形図、第９図はゴースト成分が強い場合
の信号波形図である。
２は反転増幅クランプ回路、３は同期分離回路
、４は積分回路、５は垂直発振回路、Ｃは直流成
分阻止コンデンサ、ＴＲ１は反転増幅トランジス
タ、ＴＲ２はバツフアトランジスタ、ＴＲ３は帰
還用トランジスタ。
1 to 3 show embodiments of the present invention,
FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a signal waveform diagram of each part when the ghost component is weak, and FIG. 3 is a diagram of signal waveforms of each part when the ghost component is strong. FIG. 4 is a synchronous signal processing circuit diagram. 5 to 9 show conventional examples, FIG. 5 is a circuit diagram of the conventional example, FIG. 6 is a waveform diagram of each part's signals when there is no ghost component, and FIG. 7 is a diagram of each part's signals when there is a ghost component. FIG. 8 is a signal waveform diagram when the ghost component is weak, and FIG. 9 is a signal waveform diagram when the ghost component is strong. 2 is an inverting amplifying clamp circuit, 3 is a synchronous separation circuit, 4 is an integrating circuit, 5 is a vertical oscillation circuit, C is a DC component blocking capacitor, TR1 is an inverting amplifying transistor, TR2 is a buffer transistor, and TR3 is a feedback transistor.
Claims (1)
与えられる直流成分阻止コンデンサと、 前記直流成分阻止コンデンサの他方のコンデン
サ電極側にベースが接続され該直流成分阻止コン
デンサを通過したテレビジヨン信号を反転増幅す
る反転増幅トランジスタと、 前記反転増幅トランジスタの出力部にベースが
接続されたバツフアトラスジスタと、 前記バツフアトランジスタの出力部と反転増幅
トランジスタのベースとの間に接続された帰還用
トランジスタとを具備し、 前記バツフアトランジスタの出力部に現われる
テレビジヨン信号中の同期信号成分が前記帰還用
トランジスタを介して反転増幅トランジスタ側に
帰還されて所定電位にクランプされることを特徴
とする反転増幅クランプ回路。[Claims for Utility Model Registration] A DC component blocking capacitor to which a television signal is applied to one capacitor electrode side, and a base connected to the other capacitor electrode side of the DC component blocking capacitor, and a television signal passing through the DC component blocking capacitor. an inverting amplification transistor for inverting and amplifying a television signal; a buffer atlas transistor having a base connected to the output of the inverting amplification transistor; and a buffer atlas transistor connected between the output of the buffer transistor and the base of the inverting amplification transistor. and a feedback transistor, the synchronizing signal component in the television signal appearing at the output part of the buffer transistor is fed back to the inverting amplification transistor side via the feedback transistor and clamped to a predetermined potential. Features an inverting amplification clamp circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10718485U JPS6214859U (en) | 1985-07-12 | 1985-07-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10718485U JPS6214859U (en) | 1985-07-12 | 1985-07-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6214859U true JPS6214859U (en) | 1987-01-29 |
Family
ID=30983230
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10718485U Pending JPS6214859U (en) | 1985-07-12 | 1985-07-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6214859U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63302674A (en) * | 1987-06-02 | 1988-12-09 | Matsushita Electric Ind Co Ltd | Synchronizing signal amplifier circuit |
| JPH0385970A (en) * | 1989-08-30 | 1991-04-11 | Matsushita Electric Ind Co Ltd | Clamp circuit |
| JPH05176964A (en) * | 1992-01-07 | 1993-07-20 | Yoshinori Yasuda | Medical treatment implement |
-
1985
- 1985-07-12 JP JP10718485U patent/JPS6214859U/ja active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63302674A (en) * | 1987-06-02 | 1988-12-09 | Matsushita Electric Ind Co Ltd | Synchronizing signal amplifier circuit |
| JPH0385970A (en) * | 1989-08-30 | 1991-04-11 | Matsushita Electric Ind Co Ltd | Clamp circuit |
| JPH05176964A (en) * | 1992-01-07 | 1993-07-20 | Yoshinori Yasuda | Medical treatment implement |
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