JPS59134968U - clamp circuit - Google Patents
clamp circuitInfo
- Publication number
- JPS59134968U JPS59134968U JP2777883U JP2777883U JPS59134968U JP S59134968 U JPS59134968 U JP S59134968U JP 2777883 U JP2777883 U JP 2777883U JP 2777883 U JP2777883 U JP 2777883U JP S59134968 U JPS59134968 U JP S59134968U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- clamp circuit
- emitter
- video signal
- turned
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Picture Signal Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図はこの考案の説明に供する系輯図、第２図は従来
のクランプ回路の一例を示す接続図、第３図はその動作
説明に供する波形図、第４図及び第５図は夫々この考案
に係わるビ≠オ信号のクランプ回路の一例を示す接続図
、第６図はカラーモニタ用のクランプ系を示す一例の系
統図である。
１０はクランプ回路、４は映像出力回路、１゜２は映像
増幅回路、Ｑａは第１のトランジスタ、Ｑｂは第２のト
ランジスタ、ｃｏはクランプ用コンデンサ、２０は制御
回路、２１は時定数回路、Ｒａは放電ループに挿入され
た抵抗器である。Fig. 1 is a system diagram to explain this invention, Fig. 2 is a connection diagram showing an example of a conventional clamp circuit, Fig. 3 is a waveform diagram to explain its operation, and Figs. 4 and 5 respectively. FIG. 6 is a connection diagram showing an example of a video signal clamp circuit according to this invention. FIG. 6 is a system diagram showing an example of a clamp system for a color monitor. 10 is a clamp circuit, 4 is a video output circuit, 1°2 is a video amplification circuit, Qa is a first transistor, Qb is a second transistor, co is a clamp capacitor, 20 is a control circuit, 21 is a time constant circuit, Ra is a resistor inserted into the discharge loop.
Claims (1)
サを介してビデオ信号が供給され、このエミッタより所
定電位にクランプされたビデオ信号が出力されると共に
、上記第１９トランジスタとは逆導電型の第２のトラン
ジスタが上記エミッタに接続され、上記第１のトランジ
スタがオフになったときに得られる出力で上記第２のト
ランジスタをオンするようにしたクランプ回路。 −A video signal is supplied to the emitter of the first transistor for clamping via a capacitor, and a video signal clamped to a predetermined potential is output from this emitter. A clamp circuit in which a transistor is connected to the emitter, and the second transistor is turned on with an output obtained when the first transistor is turned off. −
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2777883U JPS59134968U (en) | 1983-02-25 | 1983-02-25 | clamp circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2777883U JPS59134968U (en) | 1983-02-25 | 1983-02-25 | clamp circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59134968U true JPS59134968U (en) | 1984-09-08 |
Family
ID=30158661
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2777883U Pending JPS59134968U (en) | 1983-02-25 | 1983-02-25 | clamp circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59134968U (en) |
-
1983
- 1983-02-25 JP JP2777883U patent/JPS59134968U/en active Pending
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