JPS62146215U - - Google Patents
Info
- Publication number
- JPS62146215U JPS62146215U JP3162486U JP3162486U JPS62146215U JP S62146215 U JPS62146215 U JP S62146215U JP 3162486 U JP3162486 U JP 3162486U JP 3162486 U JP3162486 U JP 3162486U JP S62146215 U JPS62146215 U JP S62146215U
- Authority
- JP
- Japan
- Prior art keywords
- error amplifier
- converter
- signal generation
- external input
- output voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Continuous-Control Power Sources That Use Transistors (AREA)
- Dc-Dc Converters (AREA)
Description
第１図は本考案の原理を示す図、第２図は本考
案の一実施例を示す図、第３図は第２図における
デイジタル信号発生回路の詳細を示す図である。
図において、１は誤差増幅器、２は基準電圧源
、１４は出力電圧制御用トランジスタ、１５は入
力電源、１６は負荷抵抗、２１１，２１２はデイ
ジタル信号発生回路、２２１，２２２はＤ／Ａコ
ンバータ、２３は可変抵抗、２４〜２６は抵抗、
２７と２８はホトカプラ、２９は排他的論理和回
路、３０と３２は論理積回路、３１と３３は否定
回路をそれぞれ示す。
FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram showing an embodiment of the present invention, and FIG. 3 is a diagram showing details of the digital signal generation circuit in FIG. 2. In the figure, 1 is an error amplifier, 2 is a reference voltage source, 14 is an output voltage control transistor, 15 is an input power supply, 16 is a load resistor, 211 and 212 are digital signal generation circuits, 221 and 222 are D/A converters, 23 is a variable resistor, 24 to 26 are resistors,
27 and 28 are photocouplers, 29 is an exclusive OR circuit, 30 and 32 are AND circuits, and 31 and 33 are NOT circuits, respectively.
Claims (1)
前記誤差増幅器１の制御により出力電圧制御用ト
ランジスタ１４を制御する直流安定化電源回路に
おいて、外部からの入力信号によりデイジタル信
号を発生するデイジタル信号発生回路２１１，２
１２と、デイジタル信号発生回路２１１，２１２
で発生したデイジタル信号をアナログ信号に変換
する第１のＤ／Ａコンバータ２２１及び第２のＤ
／Ａコンバータ２２２を設け、該第１、第２のＤ
／Ａコンバータ２２１，２２２の吸込電流により
前記誤差増幅器１の基準電圧レベルＶＸを設定し
、前記誤差増幅器１を作動させ、前記出力電圧制
御用トランジスタ１４を制御するように構成した
ことを特徴とする電圧切替え回路。 Error amplifier 1 is activated by an external input signal,
In the DC stabilized power supply circuit that controls the output voltage control transistor 14 under the control of the error amplifier 1, digital signal generation circuits 211 and 2 generate digital signals based on external input signals.
12, and digital signal generation circuits 211 and 212
A first D/A converter 221 and a second D/A converter 221 that convert digital signals generated in
/A converter 222 is provided, and the first and second D
The reference voltage level VX of the error amplifier 1 is set by the sink current of the /A converters 221 and 222, the error amplifier 1 is operated, and the output voltage control transistor 14 is controlled. Voltage switching circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3162486U JPS62146215U (en) | 1986-03-05 | 1986-03-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3162486U JPS62146215U (en) | 1986-03-05 | 1986-03-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62146215U true JPS62146215U (en) | 1987-09-16 |
Family
ID=30837531
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3162486U Pending JPS62146215U (en) | 1986-03-05 | 1986-03-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62146215U (en) |
-
1986
- 1986-03-05 JP JP3162486U patent/JPS62146215U/ja active Pending