JPS62142472A - Horizontal synchronizing signal separating device - Google Patents

Abstract

PURPOSE:To separate digitally a horizontal synchronizing signal from a composite synchronizing signal by providing a 1/2 frequency division circuit using a leading or trailing edge of the composite synchronizing signal as an active input. CONSTITUTION:A pulse 19a decoded by an AND gate 19 is fed to a set terminal of a 1/2 frequency division circuit T-FF 20, a leading differentiation pulse 15a of the composite synchronizing signal is fed to a clock input terminal, a non- inverting output 20a and a composite synchronizing signal 1a are fed to the input terminal of an AND gate 21 and a horizontal synchronizing signal 21a is outputted from the output terminal of the AND gate 21. Then the 1/2 frequency division circuit is set (reset) by a decode output pulse during a period other than the vertical blanking period, reset (set) by the differentiation pulse of the trailing edge of the composite synchronizing signal, the non-inverting output (inverting output) of the 1/2 frequency division circuit and the composite synchronizing signal are ANDed (positive logic) to obtain a horizontal synchronizing signal, and the decode output pulse is not outputted during the vertical blanking period.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a horizontal synchronization signal separation device for separating a horizontal synchronization signal from a composite video signal.

2. Description of the Related Art Horizontal synchronization signal separation devices are provided in video equipment such as television receivers and video tape recorders (VTRs). In particular, in slow playback of a VTR, it is necessary to keep the frequency of the horizontal open 2 Hoeno phase signal constant as a means of correcting the lateral wobbling of the reproduced image due to changes in relative speed between the magnetic tape and the rotating head.
In such a case, conventionally, the part where the period of the horizontal synchronizing signal in the vertical ranking period is doubled is reduced to 1/1.
I divided it into two parts and took it out.

FIG. 6 is a diagram showing an example of such a conventional horizontal synchronization signal separation device (monostable multivibrator), in which 1 is a composite synchronization signal input terminal, 2 is a monostable multivibrator, and 3 is a horizontal synchronization signal output terminal. be. FIG. 6 is a waveform diagram showing the signals of each part in FIG. 5, and the signals corresponding to the respective terminals in FIG. 5 are indicated by the same numbers with a appended to them.

Problems to be Solved by the Invention Since the conventional horizontal synchronization separation device uses a monostable multiviprator, it cannot be integrated into an integrated circuit because it includes a capacitor as a component for setting the time constant.
There are disadvantages in that an increase in the number of parts is unavoidable when assembling the equipment, and miniaturization is not possible. SUMMARY OF THE INVENTION An object of the present invention is to provide a three-vane horizontal synchronization separation device suitable for semiconductor integrated circuits (monolithic ICs), while eliminating the drawbacks of the prior art described above.

SUMMARY OF THE INVENTION In order to achieve the above objects, the present invention provides clock pulses that are set or reset by a composite synchronization signal to
The unit horizontal synchronization signal period (1H==63
．． 5 μs) is set or reset by the signal from the AND circuit section and the AND circuit section that generates a pulse in the latter half of the 1/2 minute period, and the rising edge or falling edge of the composite synchronization signal is used as the active input. It is equipped with a circuit so that a horizontal synchronization signal can be digitally obtained from a composite synchronization signal.

In other words, during periods other than the vertical blanking period, the decoded output pulse from the counter sets (or resets) the 1/2 frequency divider, and the falling edge of the composite synchronizing signal (horizontal synchronizing signal is positive) sets (or resets) the decoded output pulse from the counter. Reset (or set) by the differential pulse, and obtain the horizontal synchronization signal by taking the AND (positive logic) of the non-inverted output (or inverted output) of the 1A frequency dividing circuit and the composite synchronization signal. ,
On the other hand, during the vertical blanking period, the decode output pulse is not output, so the 1/2 frequency divider circuit is not set (or reset), and the 1/2 frequency divider circuit inverts the output due to the differential pulse. Repeatedly, the AND output generates an output at the period of the horizontal synchronization signal. Therefore, the horizontal synchronization signal can be stably and reliably separated over the entire period of the composite synchronization signal.

EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings. FIG. 1 is a circuit configuration diagram showing an embodiment of a horizontal synchronization signal separation device according to the present invention, in which 1 is a composite synchronization signal input terminal;
4 is a clock pulse input terminal, 10, 11.12, 20
is a T-type flip-flop with set function (hereinafter referred to as T-FF)
), 13.15.16 is an inverter circuit, 14
, 17°18 is a NAND gate circuit, 19.21 is an AN
This is a D6 page gate circuit. FIGS. 2 and 3 are waveform diagrams showing signals of each part in FIG. 1, and each signal waveform is indicated by the same number as each component in FIG. 1 with the suffix "a" attached. FIGS. 2 and 3 are waveform diagrams when changing from an odd field to an even field and from an even field to an odd field, respectively. In FIGS. 1, 2, and 3, the composite synchronization signal 1a from the input terminal 1 is transmitted to the T-FFs 10, 11, .
It is input to each set terminal of a down counter consisting of 12. The counter, which is set by the positive pulse of the composite synchronizing signal 1a, counts the clock pulses 4a that are input to the input terminal 4, and is set again by the next positive pulse of the composite synchronizing signal 1a. And T-FF that constitutes the above counter
AND gate 19 into which each inverted output of 11 and 12 is input.
A passive code pulse 19a is output. In this embodiment, the frequency of the clock pulse 4a is set to 3.58M.
I chose Hz/32 (=112KHz).

The pulse 19 coded by the AND gate 19
a to the cell 6 page terminal of the 1/2 frequency divider circuit T-FF20, the falling differential pulse 15a of the composite synchronization signal to the clock input terminal, and the non-inverting output 20a.
and composite synchronization signal 1a are respectively supplied to the input terminal of AND gate 21, and output terminal of AND gate 21 outputs horizontal synchronization signal 21a.

Outside the vertical blanking period, T-FF20 lever 5
- differential pulse 1 at the falling edge of the horizontal synchronization signal (positive pulse), set by the output pulse 19a;
When 5a is input as a clock, the output is inverted. Therefore, an AND gate 2 in which the non-inverting output 20a of the T-FF 20 and the composite synchronization signal 1a are respectively connected to the input terminals.
The output 21a of No. 1 becomes the horizontal synchronizing signal itself.

On the other hand, during the vertical blanking period, the period of the horizontal synchronizing signal is doubled and the decode output pulse 19a is not output. Therefore, the output 20. of the T-FF 20 is caused by the falling differential pulse of the first signal at the beginning of the equalization pulse.
A is set to LOW level, and after that, the falling edge of the equalization pulse is repeatedly inverted by the differential pulse 7 bases, and an equalization pulse is output to the output terminal of the AND gate 21 every other time from the first pulse. be done. This operation is similar during the vertical synchronization pulse period and the equalization pulse period in the latter half thereof, and the output signal 21a of the AND gate 21 is obtained by dividing the rising edge of the composite synchronization signal 1a by 1/2. Further, even if the unit horizontal synchronizing signal period (1H) starts again after the vertical blanking period ends, the output signal 21a does not have a frequency jump.

This is because, in both odd and even fields, the number of falling edges (or rising edges) from the start of the equalization pulse through the vertical synchronization pulse to the end of the equalization pulse is always an odd number, and the output signal This is because the start and end of the equalization pulse are necessarily output to 21a.

FIG. 4 shows how to use the separated horizontal synchronization signal to form a horizontal synchronization 1/2 frequency divided output signal, a vertical synchronization signal, and a field discrimination signal at output terminals 3', 6, and 6, respectively. The digital circuit configuration is shown. The components are
All are represented according to standard symbols.

As described in detail, according to the present invention, it is possible to digitally separate the horizontal synchronization signal from the composite synchronization signal, and it is possible to realize a horizontal synchronization signal separation device that can be easily integrated into semiconductors. Also, with some additional circuitry, it is possible to separate the vertical synchronization signal from the composite synchronization signal and to perform field discrimination.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the horizontal synchronization signal separation device according to the present invention, FIGS. 2 and 3 are waveform diagrams showing signals of each part in FIG. 1, and FIG. 4 is a field to which the present invention is applied. FIG. 6 is a block diagram showing an example of a conventional horizontal synchronizing signal separation device; FIG. 6 is a waveform diagram showing signals at various parts in FIG. 6. 2... Monostable multivibrator, 10,11
゜12, 20... T-type flip-flop circuit with set function, 13, 15, 16... Inverter circuit, 9 pages 14.17, 18... NAND gate circuit, 1
9゜21...AND gate circuit.

Claims (1)

[Claims] Means for digitally obtaining a horizontal synchronization signal from the composite synchronization signal by creating a pulse that occurs in the latter half of a unit horizontal synchronization signal period by the output of a counter that is set or reset by the composite synchronization signal and counts clock pulses. A horizontal synchronization signal separation device characterized by comprising: