JPS62139062A - Data switching system - Google Patents

Abstract

PURPOSE:To secure the identity between data sent from another controller and data to which own controller accesses, by permitting the switching of banks only when a bank switching command is delivered from the own controller. CONSTITUTION:A EOR gate 5 performs an OR arithmetic operation between the outputs of a bank selection information storing bit memory 1 and a switch information storing bit memory 2. Then the gate 5 outputs H when no coincidence is obtained and outputs L when coincidence is obtained between both outputs and closes NAND gates 61 and 62 to inhibit the switching between banks A and B. Therefore, the switching information on the memory 2 is inverted and given to the memory 1 as long as the data is received normally and a switching command is given from a controller. Thus no coincidence is obtained between both outputs of memories 1 and 2 and therefore both gates 61 and 62 are opened via the gate 5. In such a way, the switching is carried out between banks according to the contents of the memory 1.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention provides a plurality of controllers that are arranged in parallel via a transmission bus, and each controller is divided according to the number of controllers and is connected to the controller via a system bus. In addition, there is a dual port memory with a 2-punk configuration that can be accessed from other controllers via a transmission bus, a switching circuit that alternately switches banks of the dual port memory, and a switching control circuit that controls this switching circuit. The present invention relates to a data exchange method in which broadcast data is exchanged between a plurality of controllers via the dual port memory.

[Conventional technology]

Conventionally, as this type of data exchange method, there is the following method proposed by the applicant (Japanese Patent Application Laid-Open No. 60-8970).
Publication No.). FIG. 4 is a block diagram showing such a system.

This is the processor (CPU) 111. ROM11
Control circuit 1 consisting of 2 and RAM 115
1, a dual port memory 7 consisting of two banks (banks) 7a and 7b, and its switching circuit '2+ + 12
2, a switching control circuit 13, and a transmission system 1 including a transmission bus.
4, this controller 10
is connected in parallel with another controller (hereinafter also simply referred to as the transmission side or transmission system) via the transmission bus of the transmission system 14, and thus constitutes a so-called multi-controller system.

Each bar of dual port memory 7 7 a r 7
b is divided into a plurality of blocks B11 to BIN t B21 to B2N corresponding to the number of controllers, BN and B21 for one controller, B12 and B22 for another controller, etc. ( Data exchange between this controller 10 and other controllers (Δ transmission system) is performed via this dual port memory 7. For example, block B11#B2
Assuming that block B11 is allocated for data exchange with the transmission system serving as controller 0, block B11
When connected to the controller 0 side to receive (read) data, block B21 is connected to the transmission system and sends (writes) data, while block BN is connected to the transmission system and sends (writes) data. When performing !(write),
Controller 0 is connected to block B21 and receives data (sequential output). Switching circuit 12+ + 122
ii. Each block in these banks is switched, and the switching control circuit 16 performs the control.

In FIG. 4, the switching circuit 12 + + 122 is shown as a layer, and the switching control circuit 16 is shown as a block, but the configuration is specifically as shown in FIG. 5. Here, 1 is a bit memory in which bank selection information is stored. 42 is a gate, 31, 52, and 33 are inversion gates, and different banks are selected depending on whether the access is from the transmission system or the controller. Note that 7 is a dual port memory divided into two banks, B.

That is, when the dual port memory 7 is accessed from the controller 10 or the transmission system, the block number corresponding to the address is specified. This block number becomes the address of the bank selection information storage bit memory 1, and bank selection information for each block is output from the bank selection information storage bit memory 1. With this information, when accessing from the controller 10 side, for example, the inversion gate 32
In addition, when accessing from the transmission system, bank A or bank B is selected through gates 42, respectively. Bank switching is performed by a switching command that is output for each block when normal data is received or when transmission data writing is completed. In other words, the contents of the bank selection information storage bit memory 1 are inverted by the inversion gate 31.
Since this simply involves switching the bank from person to B or from B to person, it is sufficient to invert the contents of memory 1 block by block.

[Problem that the invention seeks to solve]

In this way, the switching timing of the received data block for received data and the timing of data access on the controller side are completely asynchronous, so there is a problem that synchronization of the data accessed by the controller is not guaranteed. In other words, for example, as shown in Figure 6,
If the bank is switched at the time when the controller has read the bank data up to Nm words, the controller will read the data of bank B. Therefore, for data that has meaning in N words, data up to N-m is data in bank A, and subsequent data m is data in bank B, which poses a problem in that data identity or synchronization is not guaranteed. .

Therefore, an object of the present invention is to guarantee the identity of data sent from other controllers and data accessed by the own controller.

[Means for solving problems]

A first memory stores selection information for selecting a memory bank for each block, a second memory stores bank switching information, and the first memory stores memory only when data from another controller is normally received. a first gate means for storing the contents in the second memory; and a second gate means for storing the contents of the second memory in the first memory in response to a switching command from its own controller.
a first gate means; and third gate means for exclusive ORing the second memory outputs.

[Effect]

By providing a bit memory for bank selection and a bit memory for bank switching in l, the normally received data for each block is registered in this bank switching bit memory,
Furthermore, by inverting the contents of the bank switching bit memory and storing it in the bank selection bit memory based on a switching command from the controller, synchronization or identity between the transmitted data and the data accessed by the system side is ensured. .

〔Example〕

FIG. 1 is a block diagram showing an embodiment of the present invention.

As is clear from the figure, this is different from the one shown in FIG.
It is constructed by adding an exclusive OR (EOEL) gate 5, Nant gates 61, 62, etc.

The switching information storage bit memory 2 stores switching information for each block. At this time, the output of the bank selection information storage bit memory 1 is given to the memory 2 via the gate 41, but this gate is opened only when the data from the transmission system is normally received. The contents of memory 2 match the contents of memory 1 as long as it is received at

Now, for the sake of simplicity, if we focus only on the block consisting of banks A and H, if the selection information for that block is H#, the content of memory 1 is tI'i"H", and the content of memory 2 is then four blocks. If the corresponding data is received normally, it is '4H77; if it is not received normally, it is 'L#'.
It is.

On the other hand, the output of memory 2 is given to memory 1 via an inversion gate 31, but since this inversion gate 31 is opened by a switching command from the controller, the contents of memory 2 are inverted when a switching command is given. is given to memory 1. In other words, if memory 2 is "H'", memory 1 is 1L".

The EOR circuit 5 performs a logical OR operation on the outputs of the memory 1 and the memory 2, and when they do not match, it outputs @H", and when they match, it outputs "L" (Nando game) 61,
52 to prevent banks A and B from switching.

Therefore, when data is received normally and a switching command is given from the controller, the switching information in memory 2 is inverted and given to memory 1, and as a result, the outputs of memory 1 and memory 2 become inconsistent, so EOR Since Nantes gates 61 and 62 are opened via gate 5, memory 1
Depending on the contents, bank switching is performed in the same manner as in FIG. On the other hand, if data is not received normally, memory 1
Since the contents of and the contents of memory 2 match,
The output of EOR gate 5 becomes @L# and becomes Nantes gate 6.
1 and 62 are not opened, resulting in no bank switching.

FIG. 2 is an explanatory diagram for explaining the operation when reception is abnormal.

This is because data B1 was received normally as shown in the same figure (a), but when data B2 was received, a reception error occurred.
This shows a case where no switching is performed and the result (b) is that data B1 is used on the system side.

Figure 3 is for explaining the operation in the middle of data reception. Indicates the case where it is used.

As described above, as shown in Figure 1 (configuration K), switching is not performed unless a switching command is issued from the system (controller) side. This ensures the sameness of data in just a few seconds.

〔Effect of the invention〕

According to this invention, by configuring the bank control phase memory to be divided into one for storing bank selection information and one for storing switching information, the bank switching timing can be specified from the controller, and the transmission data (from other controllers) can be specified. This provides the advantage of being able to guarantee synchronization (identity) between the data being sent (data being sent) and the data being accessed by the system.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention, FIG. 2 is an explanatory diagram for explaining the operation when reception is abnormal, FIG. 6 is an explanatory diagram for explaining the operation during reception, and FIG. Fig. 5 is a block diagram showing a conventional example of a data exchange system, Fig. 5 is a block diagram showing a specific example of the dual port memory shown in Fig. 4, its switching circuit and switching control circuit, and Fig. 6 shows how transmission data and its own controller are connected. FIG. 6 is an explanatory diagram for explaining a case where data to be accessed is asynchronous. Code explanation 1... Bank selection information storage bit memory, 2.
...Switching information storage bit memory, 31, 52.5
3...inversion game), 41.42...gate, 5...EOR gate, 61.62...
...S/gate, 7...Dual port memory, 7a, 7b...Boat (bank), 10
... Controller, 11 ... Control circuit, 111 ... Processor, 112 ...
...ROM, 115...RAM, 121.
122...Switching circuit, 16...Switching control circuit, 14...Transmission system. Agent Patent attorney Akio Namiki Agent Patent attorney Matsuzaki Seihei - Kazuyoshi 2 Toro fee 1 Ura t Se1 Teku Gakugo - 7 Figure 5 Figure 6

Claims (1)

[Claims] A plurality of controllers are arranged in parallel via a transmission bus, and each controller is divided into blocks according to the number of controllers. A dual-port memory with a two-bank configuration that can be accessed by each bank, a switching circuit for alternately switching the banks of the dual-port memory, and a switching control circuit for controlling the switching circuit are provided, respectively. In a data exchange method for transmitting and receiving data between a plurality of controllers via a memory, each of the switching control circuits includes a first memory that stores selection information for selecting the memory bank for each block; , a second memory for storing bank switching information; a first gate means for storing the contents of the first memory in a second memory only when data from another controller is normally received; and bank switching information from the own controller. a second gate means for storing the contents of the second memory in the first memory in response to a switching command; and a third gate means for enabling or disabling bank switching in response to outputs from the first and second memories. . A data exchange system characterized in that bank switching is enabled only when data from at least another controller is normally received and a bank switching command is issued from the own controller.