JPS62137828A - Position aligning method - Google Patents

Abstract

PURPOSE:To improve position aligning accuracy and to shorten the required time of the alignment, by setting a reference coordinate system by an off axis method, detecting the positions of a plurality of chips, which are approximately uniformly dispersed and selected in a wafer by a TTL method, using the positions of the chips, and correcting the reference coordinate system. CONSTITUTION:A reference coordinate system is set by performing the position alignment of the entire wafer by an off axis method. Then, in order to correct the drift of the reference coordinate system, position alignment for every chip is performed by a TTL method. In this position alignment, a plurality of chips, which are approximately uniformly distributed and selected in the wafer, are used. After the position alignment for all the selected chips is performed and their positions are detected, only the reliable results of position alignment are selected. When the reliable results of the required number of position alignments are finally obtained, the reference coordinate system, which is set by the off axis method, is corrected for every chip. Thus the coordinate system of the entire wafer is set and exposure is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the manufacture of devices such as semiconductor devices and bubble devices, and particularly to a method for aligning an exposure apparatus in the wafer manufacturing process.

[Already required]

The present invention is a method for aligning an exposure apparatus in a device wafer manufacturing process, in which a reference coordinate system for the entire uniform bar is first set using an off-axis method, and then the reference coordinate system is almost uniformly distributed and selected from within the wafer using a TTL method. By detecting the positions of multiple chips that have been detected and using these detected positions to correct the reference coordinate system and perform alignment, we aim to improve alignment accuracy and shorten the required time. It is something.

[Conventional technology]

In recent years, as the density of semiconductor integrated circuit devices has increased, higher precision has been required for alignment during the manufacturing process. Conventionally, there are two methods for alignment during exposure using an exposure device such as a reduction projection transfer device in an autolithography process: an off-axis method and a TTL (Through The Lens) method. (for Institute of Electronics and Communication Engineers, rL
(Refer to SI Handbook J P4261984 Oichisha). The former performs alignment at a location away from the exposure axis, and is mainly used to align the entire wafer through holes, while the latter performs alignment on the exposure axis through a lens, and is mainly used to align each chip. Used for alignment.

[Problem that the invention seeks to solve]

In the former case, the conventional alignment method described above does not directly align the mask or wafer, so accuracy errors due to reference coordinate system drift pose a problem. In the latter case,
Since the mask and wafer are aligned directly along the exposure axis, accuracy errors due to reference coordinate system drift are not included. In addition, since positioning is performed for each chip, it is hardly affected by precision errors caused by warping or distortion of the entire wafer. Although the second point is improved over the former, since alignment is performed for each 1,000 knobs, the alignment accuracy of the chip is affected by the shape of the alignment mark in each 1,000 knobs. . Also, since alignment is performed for all chips on the wafer each time, the time required for alignment for one wafer is longer than in the former case, and the processing capacity of the exposure equipment is reduced. There are problems such as.

The purpose of the present invention is to solve the above-mentioned problems.
It is an object of the present invention to provide a positioning method capable of improving the precision of positioning and shortening the time required.

[Means for solving problems]

The alignment method of the present invention is an alignment method for exposure equipment in a device wafer manufacturing process.
A reference coordinate system for alignment of the entire wafer is set using the axis method, and then the positions of a plurality of chips selected from within the wafer are detected by using the TTL method, and the positions of the chips are detected by using the TTL method. The present invention is characterized in that the reference coordinate system is corrected and aligned by a predetermined means using the position of the chip.

Further, in the positioning method of the present invention, the predetermined means divides the plurality of chips into a plurality of groups, and when the position within this group deviates from a predetermined value, that chip is excluded. As a result, when the number of remaining chips becomes a predetermined number or less, it is preferable to add new chips, detect their positions, and correct the reference coordinate system for each chip.

Further, in the positioning method of the present invention, the predetermined means divides the plurality of chips into a plurality of groups, and when the position within this group deviates from a predetermined value, that chip is excluded. As a result, when the number of remaining chips becomes a predetermined number or less, it is preferable that the method further includes adding new chips, detecting their positions, and correcting the reference coordinate system for each group.

[Effect]

The present invention first aligns the entire wafer using an off-axis method, sets its reference coordinate system, and then uses the TTL method to determine the positions of a plurality of chips that are almost evenly distributed and selected from the entire wafer. are detected, and the reference coordinate system is corrected based on these values to perform positioning. Furthermore, in the case of this correction, the above-mentioned chips are divided into multiple groups, and the positions within the groups are compared. ) is excluded, and if the number of chips in the group becomes less than a predetermined number due to the exclusion of defective chips, another chip is added. In this way, the corrected reference coordinate system is corrected based on the positions of a plurality of chips selected to represent the entire wafer and excluding defective chips, so its accuracy is greatly improved. . Moreover, since the number of chips for position detection is smaller than the total number, the time required for the detection is also significantly reduced.

[Embodiments] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

1 to 4 are diagrams for explaining a first embodiment of the present invention, respectively. FIG. 1 is a flowchart showing the sequence of this embodiment. As shown in Figure 1, first, the entire wafer is aligned using the off-axis method and its reference coordinate system is set, and then, in order to correct the drift of this reference coordinate system, each chip is aligned using the TTL method. Perform alignment. This alignment method is performed using a plurality of chips selected to be approximately evenly distributed throughout the wafer.

FIG. 2 is an explanatory diagram showing the wafer 1 to be aligned, and the chips 2 are regularly arranged. Among them, the one with diagonal lines indicates the selected alignment chip 3 selected above. After aligning all of these selected chips 3 and detecting their positions, only the alignment results of reliable chips are selected according to the sequence shown in FIG. This sorting method is performed by dividing the chips 2 on the wafer 1 into several blocks along the boundary line 5. FIG. 2 shows an example of division into 16 blocks. These 16 blocks are named blocks A, B, C1-..., O, P, respectively, as shown in FIG. In order to clearly explain the sorting method using blocks, the case of block F indicated by diagonal lines in FIG. 3 will be taken as an example. FIG. 4 shows 49 chips 101 to 149 included in block F. Of these, the 9 chips shown with diagonal lines are 109.1) 1.1) 3.123.125.
127.137.139.141 are the selected chips used for alignment. The alignment results of the nine chips by this TTL method are each defined by the amount of deviation from the reference coordinate system obtained from the previously performed alignment result of the entire wafer 1 by the off-axis method. Assuming that the result of alignment for each chip by the TTL method is correct, this amount of deviation becomes a value such as a reference coordinate system drift in alignment by the off-axis method.

By the way, alignment errors in the off-axis method caused by reference coordinate system drift, wafer warpage, distortion, etc. are affected differently by chips that are located far apart within the same Univer. However, adjacent chips have similar trends in receiving. Therefore, since the deviation amount defined above is similar if the chips are relatively close to each other in the same block, some of the above 9-chip alignment results are used for alignment of each chip. If the result includes a result of incorrectly detecting a position device due to deterioration in the shape of the mark, etc., it can be easily recognized because it shows a different amount of deviation from other results. In fact, it is effective to find and use the average value and standard deviation of the chip alignment results within the same block for each block. For example, after calculating the average value, results that deviate from the average value by more than a certain preset tolerance value are excluded. If the standard deviation is larger than a preset reference value, there are methods to reduce the standard deviation, such as increasing the number of chips to be aligned within the same program or excluding results that increase the standard deviation.

By using the above method, we select only the reliable ones from the alignment results of the nine chips in block F.
6 chips indicated by overlapping marks and diagonal lines 109.1) 3.12
The result of 5.127.137.141 is selected. Furthermore, if there are few reliable alignment results, the number of chips to be aligned can be increased arbitrarily. Block F
In this case, the number of reliable chip alignments decreased to 6 out of 9 chips, so the number of chips to be aligned was further increased, and the final result was 9 chips 104.109 as shown by the circle in Figure 4. .1) 3.122.125.127
．． 137.141.147 is selected as a reliable alignment result. In a similar manner, reliable chip alignment results are selected for other blocks as well.

As a result, the final selected chip 4 indicated by a circle in FIG. 2 is selected as a reliable alignment result.

In the method described above, in the sequence shown in FIG. 1, after selecting reliable alignment results, it is considered whether to increase the number of chips to be aligned.

If the number of chips to be aligned is further increased, alignment is performed by the increased number of chips, and the alignment results are again sorted. Finally, once the required number of reliable die alignment results are obtained, all results in these wafers are used to first perform off-chip alignment.
Exposure is performed by correcting the reference coordinate system set by the axis method to set the coordinate system for the entire wafer.

FIG. 5 is a flowchart showing the sequence of the second embodiment of the present invention. The second embodiment differs from the first embodiment in that, as shown in FIG. 5, the reference coordinate system is finally corrected for each block using the off-axis method. As a result, the number of correction operations is reduced compared to the first embodiment, and the effect of time reduction becomes greater accordingly.

[Effects of the Invention] As explained above, the present invention detects the position of a selected chip by dispersing the reference coordinate system set by the off-axis method almost uniformly from within the wafer using the TTL method, and further detects the position of the selected chip. Chips showing defective results are removed through grouping and sorting, and the values of the required number of chips showing good results are used to correct the reference coordinate system and perform alignment. Therefore, the accuracy is greatly improved compared to conventional methods. effective. Furthermore, chip alignment using the TTL method can be performed for a selected number of chips compared to all conventional chips, which has the effect of significantly shortening the time required for alignment.

[Brief explanation of drawings]

FIG. 1 is a flowchart showing the sequence of the first embodiment of the present invention. FIG. 2, FIG. 3, and FIG. 4 are explanatory diagrams thereof. FIG. 5 is a flowchart showing the sequence of the second embodiment of the present invention. 1... Wafer, 2... Chip, 3... Selected chip, 4... Final selected chip, 5... Boundary line, A-P
···block. Patent Applicant NEC Corporation - Agent Patent Attorney Nao Takashi Ide7 ゛''・-' and. Figure 1 Kaya-Mi7i@Example 2 Figure 5

Claims (3)

[Claims] (1) In a method for aligning an exposure apparatus in a device wafer manufacturing process, an alignment reference coordinate system for the entire wafer is set using an off-axis method, and then the coordinates are almost uniformly distributed from within the wafer using a TTL method. A positioning method characterized by detecting the positions of a plurality of selected chips, and correcting the reference coordinate system by a predetermined means using the detected positions of the chips to perform positioning. (2) The predetermined means divides a plurality of chips into a plurality of groups, excludes the chip when its position within this group is out of a predetermined value, and as a result of this exclusion, the number of remaining chips is a predetermined number. 2. The positioning method according to claim 1, further comprising: replenishing the chip, detecting the position of the chip, and correcting the reference coordinate system for each chip. (3) The predetermined means divides a plurality of chips into a plurality of groups, excludes the chip when its position within the group is out of a predetermined value, and as a result of this exclusion, the number of remaining chips is a predetermined number. 2. The positioning method according to claim 1, further comprising: replenishing the chip, detecting the position of the chip, and correcting the reference coordinate system for each group.