JPH0560643B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the manufacture of devices such as semiconductor devices and bubble devices, and particularly to a method for aligning an exposure apparatus in the wafer manufacturing process.

〔overview〕

The present invention is a method for positioning an exposure apparatus in a device wafer manufacturing process. First, a reference coordinate system for the entire wafer is set using an off-axis method, and then the reference coordinate system is almost uniformly distributed and selected from within the wafer using a TTL method. By detecting the positions of multiple chips that have been detected and using these detected positions to correct the reference coordinate system and perform alignment, we aim to improve alignment accuracy and shorten the required time. It is something.

[Conventional technology]

In recent years, as the density of semiconductor integrated circuit devices has increased, higher precision has been required for alignment during the manufacturing process. Traditionally, in the autolithography process, positioning during exposure using an exposure device, such as a reduction projection transfer device, is performed off-line.
Axis (Off/Axis) method and TTL (Through)
Two methods have been adopted (The Lens) method (edited by the Institute of Electronics and Communication Engineers, "LSI Handbook" p. 426)
(See Ohmsha 1984). The former performs positioning at a location away from the exposure axis and is mainly used for positioning the entire wafer, while the latter performs positioning on the exposure axis through a lens and is mainly used for positioning each chip. used for.

[Problem that the invention seeks to solve]

In the former case, the conventional alignment method described above does not directly align the mask and the wafer, so accuracy errors due to reference coordinate system drift pose a problem. In the latter case, since the mask and wafer are aligned directly on the exposure axis, accuracy errors due to reference coordinate system drift are not included. Also, since we are aligning each chip,
It is hardly affected by accuracy errors caused by warpage and distortion of the entire wafer. While the above points are improved over the former, since positioning is performed for each chip, the positioning accuracy of the chip is influenced by the shape of the positioning mark in the chip. Also, since positioning is performed for all chips on a wafer each time, the time required for positioning one wafer is longer than in the former case, and the processing capacity of the exposure equipment is reduced. There are problems such as.

An object of the present invention is to provide a positioning method that can improve the accuracy of positioning and shorten the time required by solving the above-mentioned problems.

[Means for solving problems]

In the alignment method of the present invention, an alignment reference coordinate system for the entire wafer is set using an off-axis method, and then the positions of a plurality of chips selected from within the wafer are determined using a TTL method. In a method for aligning an exposure apparatus in a device wafer manufacturing process in which a reference coordinate system is corrected and aligned according to a predetermined procedure using the detected chip position, the predetermined procedure is as follows:
A step of dividing the selected chips into a plurality of groups for each region on the wafer, a step of excluding chips whose position is outside a predetermined value within the group, and a step of determining the remaining chips due to this exclusion. The present invention is characterized in that it includes a step of replenishing chips in the same area and detecting their positions when the number of chips falls below a predetermined number, and a step of correcting the reference coordinate system using each group or the chips of the group as a unit. do.

[Operation] The present invention first aligns the entire wafer using an off-axis method, sets its reference coordinate system, and then uses the TTL method to align a plurality of chips that are almost uniformly distributed from the entire wafer. The position is detected, and the reference coordinate system is corrected based on these values to perform alignment. Furthermore, in the case of this correction, the above-mentioned chips are divided into multiple groups, and the positions within the groups are compared. .) is excluded, and when the number of chips in the group becomes less than a predetermined number due to the exclusion of the defective chips, another chip is newly added. In this way, the corrected reference coordinate system is corrected based on the positions of a plurality of chips selected to represent the entire wafer and excluding defective chips, so its accuracy is greatly improved. . Furthermore, since the number of chips for position detection is smaller than the total number of chips, the time required for position detection is also significantly shortened.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

1 to 4 are diagrams for explaining a first embodiment of the present invention, respectively. FIG. 1 is a flowchart showing the sequence of the first embodiment. As shown in Figure 1, first, the entire wafer is aligned using the off-axis method and its reference coordinate system is set. Then, in order to correct the drift of this reference coordinate system, each chip is aligned using the TTL method. Perform alignment. This alignment method is performed using a plurality of chips selected and distributed approximately evenly across the wafer.

FIG. 2 is an explanatory diagram showing the wafer 1 to be aligned, and the chips 2 are regularly arranged. Among them, the one with diagonal lines indicates the selected alignment chip 3. After aligning all of these selected chips 3 and detecting their positions, only the alignment results of reliable chips are selected according to the sequence shown in FIG. This sorting method is carried out by dividing the chips 2 in the wafer 1 into several blocks along boundary lines 5. FIG. 2 shows an example of division into 16 blocks. These 16 blocks are blocks A, B, C, and B, respectively, as shown in Figure 3.
..., O, P. In order to clearly explain the sorting method using blocks, the case of the blocks indicated by diagonal lines in FIG. 3 will be taken as an example. In Figure 4,
49 chips included in Block F 101~
149 is shown. Of these, the 9 chips shown with diagonal lines are 109, 111, 113, 123, 125, 1
27, 137, 139, and 141 are selection chips used for alignment. 9 by this TTL method
The chip positioning results are each defined by the amount of deviation from the reference coordinate system obtained from the previously performed positioning result of the entire wafer 1 using the off-axis method. Assuming that the alignment results for each chip using the TTL method are correct, this amount of deviation will be the value of the reference coordinate system drift in alignment using the off-axis method.

By the way, alignment errors in the off-axis method caused by reference coordinate system drift, wafer warpage, distortion, etc. are affected differently as chips are located further apart within the same wafer. The trends in how the chips are received are similar. Therefore, the amount of deviation defined above is
If the chips are located relatively close to each other in the same block, their values will be similar, so there may be errors in the alignment results for the nine chips above due to deterioration in the shape of the marks used for alignment of each chip. If the results include detection results, it can be easily recognized because it shows a different amount of deviation from other results. actual,
For each block, it is advantageous to use the average value of the alignment results of the chips within the same block to determine the standard deviation. For example, after calculating the average value, results that deviate from the average value by more than a certain preset tolerance value are excluded. If the standard deviation is larger than a preset reference value, there are methods to reduce the standard deviation, such as increasing the number of chips to be aligned within the same block or excluding results that increase the standard deviation.

Using the above method, only reliable ones are selected from the alignment results of the 9 chips of block F, and the 6 chips 109, 113, 125, 127, 137, 14 shown by the overlapping circles and diagonal lines in Fig. 4 are selected.
The result of 1 is selected. Furthermore, if there are few reliable alignment results, the number of chips to be aligned can be increased arbitrarily. In the case of block F, the number of reliable chip alignment results was reduced to 6 out of 9 chips, so the number of chips to be aligned was further increased, and finally 9 chips 104 as shown by the circle in Fig. 4 were obtained. ,109,113,1
22, 125, 127, 137, 141, 147
is chosen, resulting in a reliable alignment. Reliable chip alignment results for other blocks are selected in a similar manner. As a result, the final selected chip 4 shown by the circle in Figure 2
is chosen as a reliable alignment result.

In the method described above, in the sequence shown in FIG. 1, after selecting reliable alignment results, it is considered whether to increase the number of chips to be aligned. If the number of chips to be aligned is further increased, alignment is performed by the increased number of chips, and then the alignment results are sorted again. Finally, once the required number of reliable chip alignment results have been obtained, the reference coordinate system previously set using the off-axis method is corrected using all of the results on the wafer to align the entire wafer. Set the coordinate system and perform exposure.

FIG. 5 is a flowchart showing the sequence of the second embodiment of the present invention. The second embodiment differs from the first embodiment in that, as shown in FIG. 5, the reference coordinate system is finally corrected for each block using the off-axis method. As a result, the number of correction operations is reduced compared to the first embodiment, and the time saving effect is increased accordingly.

〔Effect of the invention〕

As explained above, the present invention uses the reference coordinate system set by the off-axis method to detect the position of the selected chip by distributing it almost uniformly from within the wafer using the TTL method, and then detects the position of the selected chip by grouping. The chips that show a good result are removed, and the values of the required number of chips that show a good result are used to correct the reference coordinate system and perform alignment. Therefore, the accuracy is greatly improved compared to conventional methods. Furthermore, chip alignment using the TTL method can be performed for a selected number of chips compared to all conventional chips, which has the effect of significantly shortening the time required for alignment.

[Brief explanation of the drawing]

FIG. 1 is a flowchart showing the sequence of the first embodiment of the present invention. FIG. 2, FIG. 3, and FIG. 4 are explanatory diagrams thereof. FIG. 5 is a flowchart showing the sequence of the second embodiment of the present invention. 1...Wafer, 2...Chip, 3...Selected chip, 4...Final selection chip, 5...Boundary line, A
~P... Block.

Claims (1)

[Claims] 1. A reference coordinate system for alignment of the entire wafer is set using an off-axis method, and then, the positions of a plurality of chips selected from the wafer are approximately uniformly distributed and their positions are determined using a TTL method. In a method for aligning an exposure apparatus in a device wafer manufacturing process, the detected position of the chip is used to correct the reference coordinate system and align according to a predetermined procedure. The steps include dividing the selected chips into a plurality of groups for each region on the wafer, and excluding chips whose positions are outside a predetermined value within the group. When the number of remaining chips due to this exclusion becomes less than a predetermined number, a step of replenishing chips in the same area and detecting their position, and a step of correcting the reference coordinate system using each group or the chips of that group as a unit. An alignment method comprising: