JP3372685B2 - Semiconductor exposure equipment - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor exposure apparatus (commonly called a stepper) for performing highly accurate exposure and a reticle used for the same.

[0002]

2. Description of the Related Art Conventionally, reticles used in steppers include
As shown in FIG. 3, circuit patterns A, B, C, and D of a plurality of chips exposed in one shot are drawn in one reticle, and the peripheral portion of the exposure area (scribe Alignment marks as and bs for detecting the positions in the x-direction and the y-direction are arranged in the section. As a wafer alignment method, the alignment positions of all the shots in the wafer are obtained from the measured values of the alignment marks as and bs in several shots (sample shots) in the wafer in consideration of the balance between the productivity and the alignment accuracy. On the other hand, a method called global alignment is used to align all shots in the wafer.

[0003]

However, as the exposure size of each shot in the stepper is becoming larger, the number of step-and-repeats (commonly called the number of shots) on the wafer is very small. This is becoming a factor that restricts the selection of sample shots and deteriorates the alignment accuracy.

FIG. 4 shows an exposure layout in such a conventional technique. In this example, the layout and the position of the alignment marks as and bs of each shot are shown for a φ8 ″ (8 inch) wafer 41 when the reticle shown in FIG. 3 is used and the exposure size is 50 mm square.
In this case, as shown in FIG.
Considering that only 6 shots are arranged, and that the shots on the outer peripheral portion of the wafer have variations in resist film thickness, wafer distortion, etc., 4 shots near the center are taken as sample shots for global alignment. Only 1 s to 4 s can be selected. In this case, the span between alignment marks measured in global alignment is as short as about 50 mm, and the number of sample shots is as small as 4. Therefore, the accuracy of the shot array magnification and rotation measurement values in the wafer deteriorates.

It is possible to use shots 2s, 3s, 5s, and 6s as supplement shots in order to increase the span between the alignment marks. In this case, the mark position becomes asymmetric with respect to the wafer center, which causes It is not preferable because it causes an error. Further, it is conceivable to make the mark position different for each shot, but in that case, a measurement error occurs due to the distortion of the exposure optical system and the like, which directly deteriorates the alignment accuracy, which is also not preferable.

An object of the present invention is to provide a semiconductor exposure apparatus which can perform more accurate alignment in view of the problems of the prior art.

[0007]

Means for Solving the Problems] The semiconductor exposure apparatus of the present invention for achieving this object is achieved by a semiconductor exposure apparatus for transferring a pattern on a reticle onto a wafer, One only have a pattern of multiple chips from a plurality of chips which are transferred to the plurality of shot areas on previous SL wafer using a reticle having a alignment mark for each chip, position measurement
Multiple alignment marks that are subject to
Select flop, a plurality of chips the selected measuring the position Arai <br/> placement marks comprising, before on the basis of the measurement the position meter
And means for performing serial wafer and alignment between the reticle plurality of chips wherein the selected, the shot
Multiple chips with different relative positions to the center of the area
Characterized in that it comprises a flop.

The exposure apparatus of the present invention comprises the alignment mark for the shot center within each shot area .
The Alignment caused by differences in the relative position of the chip that
Previously storing the position measurement error at sign, measuring position meter of the alignment mark based on the stored position measurement error
It is preferable to have a means for correcting The alignment is preferably a global alignment.
The exposure apparatus of the present invention preferably further comprises means for calculating a chip magnification error or chip rotation based on the position measurement of the alignment mark, and correcting the chip magnification error or chip rotation based on the calculation result. The alignment marks for each chip of the reticle include two x-direction detection marks provided at positions facing each other around each chip, and two y-direction alignment marks.
It is preferably for direction detection.

[0009]

According to this structure, since the alignment mark pattern is provided for each chip, the degree of freedom in selecting the alignment mark is high even in the case of large screen exposure in which one shot area is large. Therefore, as compared with the conventional case where an alignment mark is provided for each shot, an alignment mark with a large distance between marks and a more symmetrical position with respect to the wafer center is selected and used as an alignment mark to be measured during global alignment. The alignment accuracy is improved. In this case, a position measurement error occurs due to the position of the alignment mark with respect to the shot center in each shot area. Therefore, by storing this in advance and correcting the measurement value of the alignment mark position with respect to the shot center based on this, the alignment accuracy can be improved. Is further improved.

Further, by measuring the alignment mark positions of a plurality of chips within one shot, the magnification error and chip rotation in the shot are measured, and by correcting these, accurate warp exposure is performed. Hereinafter, the present invention will be described in more detail through examples.

[0011]

【Example】

[Embodiment 1] FIG. 1 is a plan view of a reticle according to an embodiment of the present invention. In this reticle, as shown in the figure, alignment marks a, which measure the x-direction and the y-direction, are respectively measured for patterns A to D of a plurality of chips.
b is arranged. FIG. 2 is a plan view showing a layout and an arrangement of alignment marks a and b when using this reticle and exposing a φ8 ″ wafer with an exposure size of 50 mm square.

Conventionally, as shown in FIG. 4, only the central four-shot alignment mark could be used for global alignment, but in the case of this embodiment, as shown in FIG. The alignment marks a and b of the chips 1 to 8 can be measured as sample shots (sample chips). That is, the alignment mark in the shot can be selected in chip units. Therefore, the number of sample shots (sample chips) can be set from 4 to 8 or more,
In addition, the span of the alignment mark can be extended. As for the sample chip, the chip pattern is eclipsed on the outer periphery of the wafer, but if the alignment marks of the chips 9 to 12 to which the alignment marks a and b are exposed are measured, the span between the alignment marks can be made longer. , The accuracy can be improved.

[Embodiment 2] In Embodiment 1, as shown in FIG. 2, the alignment marks a and b in the chips 1 to 8 are arranged at different positions with respect to the shot center. For example, in shot BI in row B and column I, alignment marks a and b of chip 1 are arranged on the lower left side of the center, and in shot A-II, alignment marks a and b of chip 2 are arranged on the upper right side of the center. . Therefore, due to the distortion of the exposure optical system, the alignment mark positions a and b with respect to the center of the shot differ from shot to shot, which causes an alignment error.

Therefore, in this case, the alignment accuracy is improved by performing the following correction. That is, the amount of distortion that the exposure optical system has
Remember as a table. Then, for the measured mark position x, the distortion amount α (%) corresponding to that position is drawn from the table, and αx is set as the correction amount. As a result, the shot center can be accurately calculated regardless of the position of the alignment mark within the shot, and the alignment accuracy can be improved.

[Embodiment 3] FIG. 5 is a plan view showing a reticle according to a third embodiment of the present invention. Generally, when performing exposure by a step-and-repeat method in a stepper, an error in magnification due to an exposure optical system (hereinafter, referred to as a chip magnification error) and a rotation due to an error in a stage movement (hereinafter, referred to as chip rotation) are caused. Occurs. In a large screen exposure stepper, the influence of these two error factors becomes particularly large. Therefore, in the present embodiment, as shown in FIG. 5, alignment marks a and a ′ for position detection in the x direction and alignment marks b and b ′ for position detection in the y direction are arranged around each of the chips a to d. is doing.

FIG. 6 is a plan view showing a layout when an 8 "wafer is exposed using this reticle. In the shot B-II, the alignment marks a of tip A and tip A (or the alignment mark a of tip C and tip D) are shown. '), And the chip positions in the x direction and the y direction can be calculated by measuring the mark positions of the alignment marks b of “Chip-i” and “C” (or the alignment mark b ′ of “Chip-a” and “D”). The chip rotation can be calculated by measuring the mark positions (y direction) of the alignment mark b ′ of 1 and the alignment mark b of chip toy.

The chip magnification error can be corrected by adjusting a part of the exposure optical system. Further, the chip rotation can be corrected by rotating the wafer stage according to the calculated value of the chip rotation when step-and-repeat the wafer stage.
As a result, the alignment accuracy can be further improved even in the large screen exposure.

[Fourth Embodiment] FIG. 7 is a plan view showing a reticle according to a fourth embodiment of the present invention. FIG. 8 is a plan view showing an exposure layout when exposure is performed using this reticle. In this case, each alignment mark a,
b, a ′, and b ′ are arranged at the corners of each chip pattern on the diagonal line of the exposure area, and the span between the alignment marks in measuring the chip magnification and the chip rotation is larger than that in the third embodiment. Has become. Also in this case, the chip magnification and the chip rotation can be corrected by using the alignment marks a, b, a ′ and b ′ and performing the same measurement as in the third embodiment.

[0019]

As described above, according to the present invention, since the alignment mark pattern is provided for each chip, even when the shot area is eclipsed at the outer peripheral portion of the wafer in the exposure of a large screen with a small number of shots, It is possible to measure the alignment mark with respect to the chip on the outer peripheral portion, and it is possible to measure the alignment mark at a position symmetrical with respect to the center of the wafer. Therefore, it is possible to improve the alignment accuracy. Further, in this case, the position measurement error caused by the position of the alignment mark with respect to the shot center in each shot area is stored in advance, and the measurement value of the alignment mark position with respect to the shot center is corrected based on this, thereby further improving the alignment accuracy. Can be made.

Further, by measuring the alignment mark positions of a plurality of chips within one shot, it is possible to obtain a magnification error and chip rotation in that shot, and by correcting these, more accurate exposure can be performed. it can.

[Brief description of drawings]

FIG. 1 is a plan view of a reticle according to an embodiment of the present invention.

FIG. 2 is a diagram showing a layout when a stepper uses the reticle of FIG. 1 to perform exposure on a wafer.

FIG. 3 is a plan view of a reticle according to a conventional example.

FIG. 4 is a diagram showing a layout when exposure is performed on a wafer by a stepper using the reticle shown in FIG.

FIG. 5 is a plan view showing a reticle according to a third embodiment of the present invention.

FIG. 6 is a view showing a layout when a wafer is exposed by a stepper using the reticle shown in FIG.

FIG. 7 is a plan view showing a reticle according to a fourth embodiment of the present invention.

8 is a diagram showing a layout when a stepper uses the reticle of FIG. 5 to perform exposure on a wafer.

[Explanation of symbols]

a, b, a ', b': alignment marks, 1 to 12:
Chip, a, a, u, d: chip pattern, 41: wafer.

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A 64-39726 (JP, A) JP-A 5-259019 (JP, A) JP-A 5-19448 (JP, A) JP-A 6- 232028 (JP, A) JP-A-7-45500 (JP, A) JP-A-3-228309 (JP, A) JP-A-3-230513 (JP, A) JP-A-62-24624 (JP, A) JP 62-7129 (JP, A) JP 62-90931 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/027 G03F 1 / 08,7 / 20

Claims (5)

(57) [Claims] 1. A semiconductor exposure apparatus for transferring a pattern on a reticle onto a wafer, the multiple chips on previous SL wafer using a reticle having a alignment mark pattern for each chromatic only One chip of Among multiple chips transferred to multiple shot areas
It is provided al, an alignment mark to be position measurement
Selected chips , and the selected chips are
To measure the position of the alignment mark to Bei, measuring the position meter
Comprising means for performing alignment between the wafer and the reticle on the basis of a plurality of chips wherein the selected, to include a plurality of chips relative positions are different from each other for <br/> center within the shot region Characteristic semiconductor exposure equipment. 2. A relative position of a chip having the alignment mark with respect to a shot center in each shot area.
Said previously stored position measurement errors of the alignment marks caused by the difference, the semiconductor exposure according to claim 1, characterized in that it comprises means for correcting the measured position meter of the alignment mark based on the stored position measurement error apparatus. 3. The semiconductor exposure apparatus according to claim 1, wherein the alignment is global alignment. 4. A means for calculating a chip magnification error or chip rotation based on the position measurement of the alignment mark, and correcting the chip magnification error or chip rotation based on the calculation result. The semiconductor exposure apparatus described. 5. The alignment marks for each chip of the reticle are two for detecting the x direction and two for detecting the y direction, which are provided around the respective chips at positions facing each other. The semiconductor exposure apparatus according to claim 1 or 4, characterized in that.