JPS62136037A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS62136037A JPS62136037A JP60277458A JP27745885A JPS62136037A JP S62136037 A JPS62136037 A JP S62136037A JP 60277458 A JP60277458 A JP 60277458A JP 27745885 A JP27745885 A JP 27745885A JP S62136037 A JPS62136037 A JP S62136037A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- temperature distribution
- support substrate
- electrode
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Wire Bonding (AREA)
Abstract
Description
本発明は、半導体チップ上の端子部を支持基板上の端子
部とボンディングする半導体W’Sの製造方法に関する
。The present invention relates to a method for manufacturing a semiconductor W'S in which a terminal portion on a semiconductor chip is bonded to a terminal portion on a support substrate.
集積回路の半導体チップを支持基板上の配線導体と接続
する方法として、第2図に示すように半導体チップ1上
にバンブ電極2を設け、これを第3図に示すようにフェ
ースダウンで支持基板3の表面に形成した配線導体4と
絶縁膜5の開口部においてボンディングするフリップチ
ップ方式が知られている。バンブ電極2を、例えばはん
だで形成し、配線導体4の上のはんだ電極6と位置合わ
せし、加熱してバンブ電極2とはんだ電極6を融着させ
る。しかしこの場合、何らかの原因で第3図にAで示し
たようにバンブ電極2とはんだ電極6とが融着しない断
線部が生ずることがある。最近の高密度実装では、バン
ブ電極のピッチdははんだバンプでは450−程度、金
バンプでは110μm程度になるため、目視でこのよう
な断線を検出するのは困難であり、特に第2図に示すよ
うにチップ1上の全面にバンブ電極2が分散配置された
場合など、中心部の電極における接続不良を検出するこ
とは不可能である。As a method of connecting a semiconductor chip of an integrated circuit to a wiring conductor on a support substrate, a bump electrode 2 is provided on a semiconductor chip 1 as shown in FIG. A flip-chip method is known in which a wiring conductor 4 formed on the surface of an insulating film 3 is bonded to an opening in an insulating film 5. The bump electrode 2 is formed of, for example, solder, aligned with the solder electrode 6 on the wiring conductor 4, and heated to fuse the bump electrode 2 and the solder electrode 6. However, in this case, for some reason, a disconnection may occur where the bump electrode 2 and the solder electrode 6 are not fused together, as shown by A in FIG. In recent high-density packaging, the pitch d of bump electrodes is about 450 μm for solder bumps and about 110 μm for gold bumps, so it is difficult to visually detect such disconnections, especially as shown in Figure 2. In the case where the bump electrodes 2 are distributed over the entire surface of the chip 1, it is impossible to detect a connection failure in the central electrode.
本発明は、上述の問題を解決して半導体チップ上の端子
部と支持基板上の端子部との接続不良をヰ食出し、断線
のない半導体装置を製造する方法を提供することを目的
とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for solving the above-mentioned problems, eliminating connection failures between a terminal section on a semiconductor chip and a terminal section on a support substrate, and manufacturing a semiconductor device without disconnection. .
本発明によれば、ボンディング工程後、支持基板のチッ
プと反対側の面から加熱し、チップの支持基板と反対側
の面上の温度分布像を得て、温度分布像から支持基板と
チップ間の熱伝達中心よりボンディング位置を検知し、
それより接続不良の端子部を検出することにより、高密
度実装の場合にも容易に接続不良が検出することができ
るので、上記の目的が達成される。According to the present invention, after the bonding process, heating is performed from the surface of the support substrate opposite to the chip, a temperature distribution image is obtained on the surface of the chip opposite to the support substrate, and from the temperature distribution image, the temperature distribution between the support substrate and the chip is determined. The bonding position is detected from the heat transfer center of
By detecting a terminal portion with a poor connection, a poor connection can be easily detected even in the case of high-density packaging, so that the above object can be achieved.
本発明の実施例では、半導体チップの温度分布をチップ
表面の赤外線放射を赤外線検出器により電気信号に変換
し、温度分布像として表示するサーモグラフィ装置、日
本電子株式会社製、商品名サーモピュアを用いる。支持
基板3とのボンディングを終えたチップ1の上方にサー
モグラフィ装置のオプティカルヘッドを対向させ、基板
3の下面を加熱して第1図に示すように表示板7に温度
分布像を得る。温度分布像はチップ1の表面温度分布を
等高純で示すもので、ボンディングされた電極の部分で
は基板3からの熱伝達により温度上昇を示す同心円状像
8が得られ、例えば矢印Bで示す温度分布異常部からバ
ンブ′@、i2とはんだ電極6との接続不良を検出する
ことは容易である。In the embodiment of the present invention, a thermography device, manufactured by JEOL Ltd., trade name Thermopure, is used, which converts infrared radiation on the chip surface into an electrical signal using an infrared detector, and displays the temperature distribution of a semiconductor chip as a temperature distribution image. . An optical head of a thermography apparatus is placed above the chip 1 which has been bonded to the supporting substrate 3, and the lower surface of the substrate 3 is heated to obtain a temperature distribution image on the display plate 7 as shown in FIG. The temperature distribution image shows the surface temperature distribution of the chip 1 with uniform height, and a concentric image 8 showing a temperature rise due to heat transfer from the substrate 3 is obtained at the bonded electrode part, as shown by arrow B, for example. It is easy to detect a poor connection between the bump '@, i2 and the solder electrode 6 from the abnormal temperature distribution portion.
本発明は、半導体チップの端子部と支持基板上の端子部
とのボンディング後、支持基板からの熱伝達をチップ面
上の温度分布で測定して熱伝達のを無によりボンディン
グの不健全を検出するもので、端子部の密接配置あるい
はチップ中央部への配置の場合にも容易に検出できるた
め、半導体集結回路の高密度実装の信頼性向上に極めて
有効である。The present invention measures the heat transfer from the support substrate based on the temperature distribution on the chip surface after bonding the terminal part of the semiconductor chip and the terminal part on the support substrate, and detects the unsoundness of the bond by detecting no heat transfer. Since it can be easily detected even when the terminals are closely arranged or arranged in the center of the chip, it is extremely effective in improving the reliability of high-density packaging of semiconductor integrated circuits.
第1図は本発明の一実施例に用いる温度分布表示板の斜
視図、第2図は本発明により製造される半導体集積回路
の一例のチップの平面図、第3図は支持基板とボンディ
ングされた第2図のチップの断面図である。
1:半導体チップ、2;バンプ電極、3−、支持基板、
4:配線導体、6:はんだ電極、7:温度が沖
第2図
第3図FIG. 1 is a perspective view of a temperature distribution display board used in an embodiment of the present invention, FIG. 2 is a plan view of a chip of an example of a semiconductor integrated circuit manufactured according to the present invention, and FIG. 3 is a diagram showing a chip bonded to a support substrate. FIG. 3 is a cross-sectional view of the chip of FIG. 2; 1: Semiconductor chip, 2: Bump electrode, 3-, Support substrate,
4: Wiring conductor, 6: Solder electrode, 7: Temperature difference Figure 2 Figure 3
Claims (1)
ンディングする際に、ボンディング工程後支持基板のチ
ップと反対側の面から加熱し、チップの支持基板と反対
側の面上の温度分布像を得て、該温度分布像から支持基
板とチップ間の熱伝達中心によりボンディング位置を検
知し、接続不良の端子部を検出することを特徴とする半
導体装置の製造方法。 2)特許請求の範囲第1項記載の方法において、温度分
布像をサーモグラフィ装置によって得ることを特徴とす
る半導体装置の製造方法。[Claims] 1) When bonding a terminal portion on a semiconductor chip to a terminal portion on a support substrate, heat is applied from the side of the support substrate opposite to the chip after the bonding process, and the side of the support substrate opposite to the support substrate of the chip is heated. A method for manufacturing a semiconductor device, comprising: obtaining a temperature distribution image on the surface of the substrate, detecting a bonding position based on the center of heat transfer between the support substrate and the chip from the temperature distribution image, and detecting a terminal portion having a connection failure. . 2) A method for manufacturing a semiconductor device according to claim 1, characterized in that the temperature distribution image is obtained by a thermography device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60277458A JPS62136037A (en) | 1985-12-10 | 1985-12-10 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60277458A JPS62136037A (en) | 1985-12-10 | 1985-12-10 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62136037A true JPS62136037A (en) | 1987-06-19 |
Family
ID=17583865
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60277458A Pending JPS62136037A (en) | 1985-12-10 | 1985-12-10 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62136037A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09166422A (en) * | 1995-12-18 | 1997-06-24 | Nec Corp | Device and method for inspecting bump junction |
-
1985
- 1985-12-10 JP JP60277458A patent/JPS62136037A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09166422A (en) * | 1995-12-18 | 1997-06-24 | Nec Corp | Device and method for inspecting bump junction |
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