JPS62134744A - Address decoding system - Google Patents

Abstract

PURPOSE:To change allocation of an address of each interface from a software on a system, and to make management of an address map by a person who uses a system, unnecessary by rewriting electrically an address decoding circuit, based on an attribute data. CONSTITUTION:In case of connecting additionally an interface 3' to a bus, first of all, a software controls a program controlling circuit 22 through a bus 1, and a temporary logical data for selecting an address decoding signal 4' connected to the interface circuit 3' is written in a programmable logical element 21. When an address decoding signal 4' is selected, the interface 3' is connected electrically to the bus 1, therefore, the software reads out an attribute data 32'. The software registers the attribute data 32' which is read out, under a management of the software by control information, so that this interface 3' can be utilized from various application softwares.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an address decoding method for computer systems and the like.

2. Description of the Related Art When a plurality of interface circuits are connected to a bus in a computer system or the like, an address decoding circuit is required to allocate different addresses to each interface circuit to prevent data collisions.

The conventional address decoding circuit has address decoding circuits 33 and 33' inside each interface 3 and 3' connected to the bus 1, as shown in FIG. Keizo Moto, "Input/Output Control and System Configuration", Ohmsha, p. 11) This address decoding circuit was composed of fixed logic circuits. However, when using such an address decoding circuit composed of fixed logic circuits, it is necessary to allocate different addresses to the interface circuits connected to the bus. It is necessary to allocate addresses to all interfaces, including those that may be different, and to design individual address decoding circuits based on these addresses. However, in reality, this is not possible, and some addresses may overlap or interface connections may be restricted.

For this reason, a switch was installed in the address decoding circuit to set the address, and when connecting the interface to the bus, the switch was changed to set the address so that all addresses would not be duplicated. .

Problems to be Solved by the Invention However, with conventional address decoding circuits, the user has to manage all addresses, which is not only troublesome, but also causes device data collisions if management is neglected. This has the problem of destroying the device.

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention aims to provide an address decoding method that allows the computer system itself to manage addresses.

Means for Solving the Problems In order to achieve the above object, the present invention provides an address decoding circuit composed of electrically rewritable logic elements that decode and provide address signals to each ink face circuit, and each interface. A means for storing each attribute data is provided inside the circuit.

Effect The present invention has the above-described configuration, and based on the attribute data,
By rewriting the logic data of the logic elements 7E and changing the logic of the address decoding circuit, the system itself can be improved to avoid problems such as duplication of addresses while satisfying the conditions required by each interface. The address assignment can be changed by software.

Embodiment FIG. 1 is a block diagram showing an embodiment of an address decoding circuit implementing the address decoding method of the present invention.

In FIG. 1, 1 is a bus for addresses, data, and control signals of a CPU, etc., 2 is an address decoding circuit that exists in one or more systems, and a programmable logic element 21 that can electrically rewrite logic data and this programmable logic This circuit includes a program control circuit 22 that rewrites the logical data of the element 21. Also, 3 and 3
' is an interface circuit connected to the bus, which includes devices 31 and 31', attribute data 32 and 32',
When an address is assigned to an address space ball by the address decode signals 4 and 4' obtained by decoding the address and control signal from the CPU by the address decode circuit 2, and the address decode signal with χ·1 center is selected. The device and attribute data are electrically connected to the bus, making it possible to read and write the data.

First, the case of additional connection to the interface 3' bus will be explained using FIG. First, the software runs the entire bus 1 to program θ1j circuit 22K DII.
L, a temporary logic 111j data 1) is loaded into the programmable logic element 21 to select the address decode signal 4' connected to the interface circuit 3'.

When the address decode signal 4' is selected, the interface 3' is electrically connected to the bus 1, so that the software reads the attribute data 32'.

The attribute data is stored as a circuit in means such as ROM, and the data necessary to control the interface and the programmable logic element 2 of the address decoding circuit
This is the data necessary to program 1. The former is
Collateral information such as data that identifies the control program itself that controls the interface or the control program stored in main memory or auxiliary memory, and the latter includes address decoding such as the number of address bytes required by the interface. Program information necessary to program the programmable logic elements of the circuit.

Since the address map is created by automatically arranging each interface by software based on the above attribute data, address information is not required on each interface.

The software registers the read attribute data 32' under control information based on the control information, and uses the interface 3 from various types of application software.
’ to be available. In addition, from the address map so far, it searches for empty addresses that do not match the addresses of interface 3, etc. that have been connected until now, and then retrieves program information from them to connect interface 3.
3', and allocates that address to interface 3' to create a new address map. Based on this address map, the program control circuit 22 is controlled to erase the logic data previously written in the programmable logic element 21 and write new logic data.

Effects of the Invention The present invention allows the address assignment of each interface to be changed from the software on the system by electrically changing the address decoding circuit based on attribute data, so that the person using the system can manage the address map. There is no need to do this, and the system itself can handle the address mapping, which is extremely useful in practice.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an address decoding circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional address decoding circuit. 1...Bus, 2...Address lever-1
'Circuit, 3...Interface, 21...
- Programmable logic element, 22... Program control circuit, 31... Device, 32...
...Attribute data. Name of representative: Patent attorney Toshio Nakao and one other person

Claims (1)

[Claims] In a computer system where multiple interface circuits are connected to a bus, an address decoding circuit consisting of an electrically rewritable logic element that decodes and provides an address signal to each interface circuit and a program control circuit that controls rewriting. and means for storing respective attribute data inside each interface circuit, and by electrically rewriting the address decoding circuit based on the attribute data, address assignment of each interface can be changed from software on the system. An address decoding method that is characterized by the following features: