JPS62130429A - Recognizing device for read data - Google Patents

Recognizing device for read data

Info

Publication number
JPS62130429A
JPS62130429A JP60271131A JP27113185A JPS62130429A JP S62130429 A JPS62130429 A JP S62130429A JP 60271131 A JP60271131 A JP 60271131A JP 27113185 A JP27113185 A JP 27113185A JP S62130429 A JPS62130429 A JP S62130429A
Authority
JP
Japan
Prior art keywords
data
output
match
microcomputers
read
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60271131A
Other languages
Japanese (ja)
Inventor
Satoshi Baba
敏 馬場
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Home Electronics Ltd
NEC Corp
Original Assignee
NEC Home Electronics Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Home Electronics Ltd, Nippon Electric Co Ltd filed Critical NEC Home Electronics Ltd
Priority to JP60271131A priority Critical patent/JPS62130429A/en
Publication of JPS62130429A publication Critical patent/JPS62130429A/en
Pending legal-status Critical Current

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  • Retry When Errors Occur (AREA)
  • Hardware Redundancy (AREA)

Abstract

PURPOSE:To prevent an erroneous fail safe due to a data read error by judging such a case to be trouble that output dissidence between two microcomputers exceeds the prescribed number of times. CONSTITUTION:After data read through input ports P10-P1n and P10'-P1n' are processed, they are outputted to output ports P20-P2n and P20'-P2n'. then an arithmetic result comparison detection means 2 compares the outputs. If they are coincident with each other, a device targeted in a controller group 6 is controlled, and next data is read. If they are dissident with each other, data are again readout and compared. If said loop is repeated over the prescribed number of times, it is judged to be the trouble, and a trouble discrimination means 4 operates the fail safe to stop the overall controller. If the arithmetic results are coincident with each other before said loop is executed less than the prescribed number of times, it is judged to be normal, and the next data is readout.

Description

【発明の詳細な説明】 (産業上の利用分野) この発明は読み込みデータ確認装置に関するものである
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a read data confirmation device.

〔従来の技術〕[Conventional technology]

近年の電子制御装置においては、多機能性、正確性およ
び信頼性を高かめ、より構成が簡11で汎用性のあるマ
イクロコンピュータを使用している。
BACKGROUND ART In recent years, electronic control devices have increased multifunctionality, accuracy, and reliability, and use microcomputers that have a simpler configuration and are more versatile.

しかし、ノイズ等によりマイクロコンピュータの暴走等
による故障が1発生したり、データを正確に読み取れな
かった場合は、電子制御装置全体が動作しなかったり誤
動作する時があった。そこで、このJこうむ非常時を考
慮しより信頼性を高めるためにマイクロコンピュータを
2個並列に接続し、2個のマイクロコンピュータの出力
が一致しない時に電子制6aB置が故障したものと判断
してフェールセーフを実行している。
However, if a failure occurs due to a runaway of the microcomputer due to noise or the like, or if data cannot be read accurately, the entire electronic control device may not operate or malfunction. Therefore, in order to improve reliability in consideration of this emergency situation, two microcomputers were connected in parallel, and when the outputs of the two microcomputers did not match, it was determined that the electronic control unit 6aB had failed. Running failsafe.

(解決しようどする問題点〕 上述したように従来の電子制御II波装置、動作の信頼
性を高めるために2個のマイクロコンピュータをilP
列に接続し、それぞれのマイクロコンピュータの出力が
一致しなかった場合を電子制御装置の故障と判断してフ
ェールセ−フを実行していた。その結果、電子制御装置
を構成している素子及び部品等の特性のばらつきや外部
ノイズ等により2mのマイクロコンピュータのデータを
読み込むタイミングがずれて出力が一致せず電子制御1
1vi置の故障と誤判断してミスフェールセフが実行さ
れていた。
(Problem to be solved) As mentioned above, in order to improve the reliability of the operation of the conventional electronically controlled II wave device, two microcomputers are installed in the ilP.
When the outputs of the respective microcomputers did not match, it was determined that there was a failure in the electronic control unit and a fail-safe was implemented. As a result, due to variations in the characteristics of the elements and parts that make up the electronic control unit, external noise, etc., the timing of reading the data from the 2m microcomputer was shifted, and the outputs did not match.
A mis-fail safe was executed, erroneously determining that there was a failure at 1vi.

この発明は上記の問題点を解消するためになされたもの
で、2個のマイクロコンピュータの出力が一致しない場
合直らに′?δ子制御装置の7エールセーフを実行づる
のではなく、2個のマイクロコンピュータより出力され
た演算結果が一致ツろまでデータを設定回数読み込み、
設定値数」二読み込んでも一致しない場合にフェールセ
ーフを実行しミスフェールセフをなくずことができる読
み込みデータ確認装置を提供することを目的とするもの
である。
This invention was made to solve the above problem, and when the outputs of two microcomputers do not match, '? Rather than executing the 7 ale safe of the delta control device, the data is read a set number of times until the calculation results output from the two microcomputers match.
It is an object of the present invention to provide a read data confirmation device capable of executing a fail-safe and eliminating a mistake-fail-safe when they do not match even after reading two set values.

(問題点を解決するための手段) 上記の目的を達成する!こめに、この発明の読み込みデ
ータ確認装置は、データを受けて同一の演算、制御等を
行ない演算結果を出力するマイクロコンピュータ2個を
入力及び出力に対して並列に接続し、該2個のマイクロ
コンピュータより出力されたそれぞれの演算結果を受け
て両演算結果を比較し一致した場合には演算結果一致記
号を出力し不一致の場合には演算結果不一致記号を出力
する演算結果比較検出手段と、該演算結果比較検出手段
より出力された演算結果不一致記号を受けて再びデータ
を読み込みlyJ記演算演算結果比較検出手段り演算結
果を比較確認し前記2個のマイクロコンピュータより出
力された演算結果が一致するまでデータを設定回教読み
込み繰り返すデータ読み込み確認手段と、該データ読み
込み確認手段によるデータの読み込み回数が回数が設定
値以上である場合を前記マイクロコンピュータ及び周辺
装置が故障したと判断し故障信号を出力する故障判断手
段と、該故障判断手段より出力された故障信号を受けて
前記2個のマイクロコンピュータの動作を停止し停止信
号を出力する停止手段とを備えて構成した。
(Means to solve the problem) Achieve the above purpose! In particular, the read data confirmation device of the present invention has two microcomputers that receive data, perform the same calculations, control, etc., and output the calculation results, and are connected in parallel to input and output. an operation result comparison and detection means for receiving each operation result output from the computer and comparing the two operation results and outputting an operation result matching symbol if they match, and outputting an operation result mismatching symbol if they do not match; Upon receiving the calculation result discrepancy symbol output from the calculation result comparison and detection means, the data is read again and the calculation results are compared and confirmed by the calculation result comparison and detection means, and the calculation results output from the two microcomputers match. a data reading confirmation means that repeats data reading until the data is read; and if the number of times the data is read by the data reading confirmation means exceeds a set value, it is determined that the microcomputer and peripheral devices have failed, and a failure signal is output. The device is configured to include a failure determining means, and a stopping means for receiving a failure signal output from the failure determining means, stopping the operation of the two microcomputers, and outputting a stop signal.

〔作用〕[Effect]

上述したように、この発明の読み込みデータ確Wffi
 R置においでは、データを受けて同一の演算。
As mentioned above, the read data confirmation Wffi of the present invention
In the R position, the data is received and the same calculation is performed.

制御II等を行ない演算結果を出力するマイクロコンピ
ュータ2個を入力及び出力に対して並列に接続し、演算
結果比較検出手段によって2四のマイクロコンピュータ
より出力されたそれぞれの演算結果を受けて両演算結果
を比較し一致した場合には演障結果一致fa号と演算結
末を出力し不一致の場合に演算結果不一致信号を出力し
、データ読み込み確認手段によって演算結果比較検出手
段にり出ノjされた演算結果不一致信号を受けて再びデ
ータを読み込み演算結果を比較確認し2個のマイクロコ
ンピュータより出力された演算結果が一致するまでデー
タを設定回数読み込み繰り返し、故障判断手段によって
データ読み込み確認手段によるデータの読み込み回数が
設定値以上である場合を前記マイクロコンピュータ及び
周辺装置が故障したと判断し故障信号を出力し、停止手
段によって故障判断手段より出力された故障信号を受け
で2個のマイクロコンピュータの動作を停止し停止信号
を出力する。
Two microcomputers that perform control II, etc. and output calculation results are connected in parallel to the input and output, and the calculation result comparison and detection means receives the calculation results output from the 24 microcomputers and performs both calculations. The results are compared, and if they match, the performance result match signal and calculation result are output, and if they do not match, a calculation result mismatch signal is output, and the data reading confirmation means outputs the calculation result comparison detection means. Upon receiving the calculation result discrepancy signal, the data is read again and the calculation results are compared and confirmed.The data is read and repeated a set number of times until the calculation results output from the two microcomputers match, and the failure judgment means reads the data. If the number of readings exceeds a set value, it is determined that the microcomputer and peripheral devices have failed, and a failure signal is output, and the stopping means operates the two microcomputers upon receiving the failure signal output from the failure determining means. and outputs a stop signal.

〔実施例〕〔Example〕

次にこの発明の実施例について図面を参照して説明する
Next, embodiments of the invention will be described with reference to the drawings.

第1図はこの発明の読み込みデータ確認装置の実施例の
配線図である。
FIG. 1 is a wiring diagram of an embodiment of the read data confirmation device of the present invention.

図示した読み込みデータ確認装置は、データを入力ポー
トより受けて同一の演算、制御等を行ない演算結果を出
力ボート出力し入力及び出力に対して並列に接続された
マンクロコンピユータ1゜1′と、マイクロコンピュー
タ1,1−の出力ポートP2o  〜Pz6.  P 
−ha  〜P−:L4より出力された演算結果を受け
て両演算結果を比較し一致した場合に演算結果一致信号
と演算結果を出力し不一致の場合には演算結果不一致信
号を出力する演算結果比較検出手段2と、演算結果比較
検出手段2より出力されfC演算結果不不一致号を受け
て再びマイクロコンピュータ1.1′の入力ポートP4
〜P1.6 + P −10−P −16よりデータを
読み込み演算結果比較検出手段2により演算結果が一致
するまでデータを設定回数読み込み繰り返すデータ読み
込み確認手段3と、データ読み込み確認手段3によるデ
ータの読み込み回数が設定値以上である場合をマイクロ
コンピュータ1.1−及び周辺装はが故障したと判断し
故障信号を出力する故障判断手段4と、故障判断手段4
より出力された故障信号をを受けてマイクロコンピュー
タ1.1−の動作を停止し停止信号を出力しマイクロコ
ンピュータ1,1−の入カポ−1−P4L、 P、−に
入力する停止手段5とより構成されている。
The illustrated read data confirmation device receives data from an input port, performs the same calculations, controls, etc., outputs the calculation results to an output port, and is connected in parallel to the input and output ports. Output ports P2o to Pz6 of the microcomputers 1 and 1-. P
-ha ~P-: Receiving the calculation result output from L4, comparing both calculation results, if they match, outputs the calculation result match signal and the calculation result, and if they do not match, outputs the calculation result mismatch signal. The comparison detection means 2 and the input port P4 of the microcomputer 1.1' are outputted from the calculation result comparison detection means 2 and receive the fC calculation result discrepancy signal.
~ P1.6 + P -10 - P -16 reads data and repeats reading the data a set number of times until the calculation results match with the calculation result comparison detection means 2 Data reading confirmation means 3 and data reading confirmation means 3 failure determination means 4 which determines that the microcomputer 1.1- and peripheral equipment has failed when the number of readings exceeds a set value and outputs a failure signal; and failure determination means 4;
a stop means 5 which stops the operation of the microcomputer 1.1- in response to the failure signal output from the microcomputer 1.1-, outputs a stop signal, and inputs the stop signal to the input ports-1-P4L, P4- of the microcomputer 1,1-; It is composed of

演算結果比較検出手段2の演算結果の比較部(よ論理積
回路a。〜aへによって構成され必要ビットの個数論理
積回路a0〜aユを用いている。
The computation result comparison section of the computation result comparison/detection means 2 is constituted by AND circuits a to a, and uses AND circuits a0 to aY of the necessary bits.

データ読み込み確認手段3.故障判断手段4゜停止手段
5は例えばマイクロコンピュータ1によって実行されて
いる。
Data loading confirmation means 3. The failure determining means 4 and the stopping means 5 are executed by the microcomputer 1, for example.

6はそれぞれ制御される目的の制!jfl ’a ’!
J f!Bである。
6 is the control of each controlled purpose! jfl 'a'!
Jf! It is B.

次にこの実施例の動作を第2図に示した動作フローチャ
ー1〜を参照しつつ説明する。
Next, the operation of this embodiment will be explained with reference to the operation flowchart 1 to 1 shown in FIG.

ステップS1より動作が開始されると、ステップS2で
制御装置全体が初期化され、S3でマイクロコンピュー
タ1.1′の入力ポートP1.〜P、。
When the operation starts in step S1, the entire control device is initialized in step S2, and the input port P1.1 of the microcomputer 1.1' is initialized in step S3. ~P.

+ P −10” P−tmよりデータを読み込む、ス
テップS4で入力ポートP tO〜P、 、 P−、o
−P −、。
+P-10" Read data from P-tm, input ports PtO~P, , P-, o in step S4
-P-,.

より読み込まれたそれぞれのデータは目的の処理により
結果を算出し、ステップS5に移り出力ポートP 26
 ””” 2a* P −、to  〜P−xtn−よ
り結果を出力づ−る。次にステップS6で演算結果比較
検出手段2によって演算結果を比較する。比較された結
果が一致している場合ステップS7に移り制御装置郡6
の目的の装置を演算結果により制御するか企判断して、
ステップS8で出力し、再びステップS3にもどりデー
タを読み込み次の動作の制御を実行する。
Each piece of data read in is subjected to the intended processing to calculate the result, and the process moves to step S5 to the output port P26.
""" 2a* Output the result from P-, to ~P-xtn-.Next, in step S6, the calculation results are compared by the calculation result comparison detection means 2.If the compared results match Control device group 6 moves to step S7.
Decide whether to control the target device based on the calculation result,
The data is output in step S8, and the process returns to step S3 to read the data and control the next operation.

ステップS6で演算結果比較検出手段2によって演算結
果を比較した結果不一致であった場合はステップS9に
移り■びステップS3にもどりデータを読み込み演算結
果の一致を判断する。このループを設定回教以上、繰り
返した場合は故障判断手段4によりマイクロコンピュー
タ1.1′又は周3H装置が故障したと判断してステッ
プS10に移りフェールセーフを作動させてステップS
11で制御装置全体を停止させる。
In step S6, when the calculation results are compared by the calculation result comparison and detection means 2 and there is no match, the process moves to step S9 and returns to step S3 to read data and determine whether the calculation results match. If this loop is repeated for more than the set time, the failure determination means 4 determines that the microcomputer 1.1' or the 3H device has failed, and the process moves to step S10, where the failsafe is activated and step S
At step 11, the entire control device is stopped.

ステップS9の故障判断手段4でループが設定回数以内
の内に演算結果が一致した場合はデータを読み込むタイ
ミングがずれて演算結果が一致しないものと判断し、フ
ェールセーフは実行されることはない。
If the calculation results match within the set number of loops, the failure determining means 4 in step S9 determines that the data reading timing is shifted and the calculation results do not match, and fail-safe is not executed.

入力ビツト数は任意に変更できることは言うよでもない
Needless to say, the number of input bits can be changed arbitrarily.

〔効果〕〔effect〕

以上説明したように、この発明の読み込みデータ確認装
置は、2個のマイクロコンピュータの演算結果を比較す
る演算結果比較検出手段と、演算結果が一致するまで設
定回数データを読み込み繰り返りデータ読み込み確認手
段と、データ読み込み回数によりデータの読み込み時の
入力誤差かマイクロコンピュータ又は周辺Ve置の故障
かを判断する故障判断手段と、停止手段とにより構成し
たので、2個のマイクロコンピュータの出力が一致しな
い場合直ちに電子制(II装置のフェールセーフを実行
することがなくなり、データの読み込み誤差かマイクロ
コンピュータ又は周辺装置の故障かを判断できるのでデ
ータの読み込み誤差にるミスフェールセーフをなくすこ
とが可能となる。
As explained above, the read data confirmation device of the present invention includes a calculation result comparison detection means for comparing the calculation results of two microcomputers, and a data read confirmation means for repeatedly reading data a set number of times until the calculation results match. , a failure determination means that determines whether it is an input error during data reading based on the number of times the data is read or a failure in the microcomputer or the surrounding equipment, and a stop means, so that if the outputs of the two microcomputers do not match, There is no need to immediately execute the fail-safe of the electronic system (II device), and it is possible to determine whether it is a data reading error or a failure of the microcomputer or peripheral equipment, making it possible to eliminate the error fail-safe caused by data reading errors.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の実施例の回路図、第2図はこの発明
の実施例の動作フローチャートである。 1.l−・・・マイクロコンピュータ、2・・・演算結
果比較検出手段、 3・・・データ読み込み確認手段、 4・・・故VJ刊断手段、 5・・・停止手段。 出願人 日木電気ホームエレク1−ロニクス株式会社 代理人 弁理士 増 1)竹 夫 第1図
FIG. 1 is a circuit diagram of an embodiment of the invention, and FIG. 2 is an operation flowchart of the embodiment of the invention. 1. 1-... Microcomputer, 2... Calculation result comparison detection means, 3... Data reading confirmation means, 4... Late VJ publication cutting means, 5... Stopping means. Applicant: Niki Denki Home Electronics Co., Ltd. Agent: Patent Attorney Masu 1) Takeo Figure 1

Claims (1)

【特許請求の範囲】 1、データを受けて同一の演算、制御等を行い演算結果
を出力するマイクロコンピュータ2個を入力及び出力に
対して並列に接続し、 該2個のマイクロコンピュータより出力されたそれぞれ
演算結果を受けて両演算結果を比較し一致した場合には
演算結果一致信号と演算結果を出力し不一致の場合には
演算結果不一致信号を出力する演算結果比較検出手段と
、 該演算結果比較検出手段より出力された演算結果不一致
信号を受けて再びデータを読み込み前記演算結果比較検
出手段により演算結果を比較確認し前記2個のマイクロ
コンピュータより出力された演算結果が一致するまでデ
ータを設定回数読み込み繰返すデータ読み込み確認手段
と、 該データ読み込み確認手段によるデータ読み込み回数が
設定値以上である場合を前記マイクロコンピュータ及び
周辺装置が故障したと判断し故障信号を出力する故障判
断手段と、 該故障判断手段より出力された故障信号を受けて前記2
個のマイクロコンピュータの動作を停止し停止信号を出
力する停止手段とを備えて構成したことを特徴とする読
み込みデータ確認装置。 2、前記演算結果検出手段は、論理積回路により構成し
たことを特徴とする特許請求の範囲第1項に記載の読み
込みデータ確認装置。
[Claims] 1. Two microcomputers that receive data, perform the same calculations, control, etc., and output the calculation results are connected in parallel to the input and output, and the output from the two microcomputers is and an operation result comparison and detection means for receiving the respective operation results and comparing the two operation results, and outputting an operation result matching signal and the operation result when they match, and outputting an operation result mismatch signal when they do not match; Upon receiving the calculation result mismatch signal output from the comparison detection means, the data is read again and the calculation results are compared and confirmed by the calculation result comparison and detection means, and the data is set until the calculation results output from the two microcomputers match. a data reading confirmation means for repeating the data reading a number of times; a failure determination means for determining that the microcomputer and peripheral devices have failed and outputting a failure signal when the number of data readings by the data reading confirmation means is equal to or greater than a set value; Upon receiving the failure signal output from the determining means,
1. A read data confirmation device comprising a stop means for stopping the operation of each microcomputer and outputting a stop signal. 2. The read data confirmation device according to claim 1, wherein the calculation result detection means is constituted by an AND circuit.
JP60271131A 1985-12-02 1985-12-02 Recognizing device for read data Pending JPS62130429A (en)

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Application Number Priority Date Filing Date Title
JP60271131A JPS62130429A (en) 1985-12-02 1985-12-02 Recognizing device for read data

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JPS62130429A true JPS62130429A (en) 1987-06-12

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05120047A (en) * 1991-05-13 1993-05-18 Railway Technical Res Inst Complete clock synchronous type duplex circuit
JP2016110502A (en) * 2014-12-09 2016-06-20 株式会社デンソー Electronic controller

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56118101A (en) * 1980-02-22 1981-09-17 Yokogawa Hokushin Electric Corp Automatic restarting system for process controller
JPS56121151A (en) * 1980-01-30 1981-09-22 Siemens Ag 2 channel data processor
JPS57196364A (en) * 1981-05-27 1982-12-02 Hitachi Ltd Free-running dual control system
JPS5837750A (en) * 1981-08-28 1983-03-05 Hitachi Ltd Fail safe circuit
JPS58223841A (en) * 1982-06-23 1983-12-26 Hitachi Ltd Data input processor of automatic plant control system

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56121151A (en) * 1980-01-30 1981-09-22 Siemens Ag 2 channel data processor
JPS56118101A (en) * 1980-02-22 1981-09-17 Yokogawa Hokushin Electric Corp Automatic restarting system for process controller
JPS57196364A (en) * 1981-05-27 1982-12-02 Hitachi Ltd Free-running dual control system
JPS5837750A (en) * 1981-08-28 1983-03-05 Hitachi Ltd Fail safe circuit
JPS58223841A (en) * 1982-06-23 1983-12-26 Hitachi Ltd Data input processor of automatic plant control system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05120047A (en) * 1991-05-13 1993-05-18 Railway Technical Res Inst Complete clock synchronous type duplex circuit
JP2016110502A (en) * 2014-12-09 2016-06-20 株式会社デンソー Electronic controller

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