JPS57196364A - Free-running dual control system - Google Patents

Free-running dual control system

Info

Publication number
JPS57196364A
JPS57196364A JP56079305A JP7930581A JPS57196364A JP S57196364 A JPS57196364 A JP S57196364A JP 56079305 A JP56079305 A JP 56079305A JP 7930581 A JP7930581 A JP 7930581A JP S57196364 A JPS57196364 A JP S57196364A
Authority
JP
Japan
Prior art keywords
computer
free
control system
dual control
synchronization
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56079305A
Other languages
Japanese (ja)
Other versions
JPS6343779B2 (en
Inventor
Manabu Sasamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56079305A priority Critical patent/JPS57196364A/en
Publication of JPS57196364A publication Critical patent/JPS57196364A/en
Publication of JPS6343779B2 publication Critical patent/JPS6343779B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To elevate operation efficiency and reliability, by separating a faulty system, or retrying a computer in case when the fault is intermittent. CONSTITUTION:Computers 1A, 1B connected to only a synchronization collating device 6 are not connected to each other, and execute the processing in the same way as a stand-alone computer. For instance, information inputted from each equipment 4 is divided and inputted to each computer 1A, 1B from the device 6, and each computer 1A, 1B execute the processing quite freely on the input information. Subsequently, output information of the computers 1A, 1B is returned to the device 6, synchronization of the timing is taken by the device 6, the output information is collated, and is outputted to the equipment 4.
JP56079305A 1981-05-27 1981-05-27 Free-running dual control system Granted JPS57196364A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56079305A JPS57196364A (en) 1981-05-27 1981-05-27 Free-running dual control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56079305A JPS57196364A (en) 1981-05-27 1981-05-27 Free-running dual control system

Publications (2)

Publication Number Publication Date
JPS57196364A true JPS57196364A (en) 1982-12-02
JPS6343779B2 JPS6343779B2 (en) 1988-09-01

Family

ID=13686126

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56079305A Granted JPS57196364A (en) 1981-05-27 1981-05-27 Free-running dual control system

Country Status (1)

Country Link
JP (1) JPS57196364A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6022265A (en) * 1983-07-19 1985-02-04 Meidensha Electric Mfg Co Ltd First-in first-out buffer device
JPS62130429A (en) * 1985-12-02 1987-06-12 Nec Home Electronics Ltd Recognizing device for read data
JPS6341943A (en) * 1986-08-08 1988-02-23 Nec Corp Error restoring system for logic unit
JPH04358234A (en) * 1991-06-04 1992-12-11 Toshiba Corp Supervisory and control method for duplex computer system
JP2011123756A (en) * 2009-12-11 2011-06-23 Toshiba Corp Safety control device and safety control program therefor

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS578868A (en) * 1980-06-17 1982-01-18 Mitsubishi Electric Corp Parallel system of electronic computer

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS578868A (en) * 1980-06-17 1982-01-18 Mitsubishi Electric Corp Parallel system of electronic computer

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6022265A (en) * 1983-07-19 1985-02-04 Meidensha Electric Mfg Co Ltd First-in first-out buffer device
JPH059822B2 (en) * 1983-07-19 1993-02-08 Meidensha Electric Mfg Co Ltd
JPS62130429A (en) * 1985-12-02 1987-06-12 Nec Home Electronics Ltd Recognizing device for read data
JPS6341943A (en) * 1986-08-08 1988-02-23 Nec Corp Error restoring system for logic unit
JPH04358234A (en) * 1991-06-04 1992-12-11 Toshiba Corp Supervisory and control method for duplex computer system
JP2011123756A (en) * 2009-12-11 2011-06-23 Toshiba Corp Safety control device and safety control program therefor

Also Published As

Publication number Publication date
JPS6343779B2 (en) 1988-09-01

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