JPS6213027U - - Google Patents
Info
- Publication number
- JPS6213027U JPS6213027U JP10408585U JP10408585U JPS6213027U JP S6213027 U JPS6213027 U JP S6213027U JP 10408585 U JP10408585 U JP 10408585U JP 10408585 U JP10408585 U JP 10408585U JP S6213027 U JPS6213027 U JP S6213027U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- pulse
- shift register
- contact
- expected value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005070 sampling Methods 0.000 claims 2
- 238000010521 absorption reaction Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Manipulation Of Pulses (AREA)
- Keying Circuit Devices (AREA)
Description
第１図は本考案の一実施例のブロツク図、第２
図は上記実施例の動作説明に供するチヤツターの
小さい場合の第１図の各部の波形図、第３図は同
じく上記実施例の動作説明に供するチヤツターの
大きい場合の第１図の各部の波形図である。
１１……タイミング発生回路、１２……シフト
レジスタ、１３……期待値マツチ回路。
Fig. 1 is a block diagram of an embodiment of the present invention;
The figure is a waveform diagram of each part in Figure 1 when the chatter is small, which is used to explain the operation of the above embodiment, and Figure 3 is a waveform diagram of each part in Figure 1 when the chatter is large, which is also used to explain the operation of the above embodiment. It is. 11...Timing generation circuit, 12...Shift register, 13...Expected value matching circuit.
Claims (1)
スのパルス受信回路において、一定周期のサンプ
リングパルスを発生するタイミング発生回路と、
上記接点のオンに伴うパルス波形の入力信号を前
記タイミング発生回路からサンプリングパルスに
よりサンプリングし保持するシフトレジスタと、
該シフトレジスタに保持した出力と期待値の照合
をとる期待値マツチ回路とを具備することを特徴
とするチヤツター吸収回路。 In a pulse receiving circuit for pulses generated by a relay contact or a switch contact, a timing generation circuit generates a sampling pulse of a constant period;
a shift register that samples and holds a pulse waveform input signal from the timing generation circuit using a sampling pulse when the contact is turned on;
A chatter absorption circuit comprising an expected value matching circuit that matches an output held in the shift register with an expected value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10408585U JPS6213027U (en) | 1985-07-10 | 1985-07-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10408585U JPS6213027U (en) | 1985-07-10 | 1985-07-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6213027U true JPS6213027U (en) | 1987-01-26 |
Family
ID=30977253
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10408585U Pending JPS6213027U (en) | 1985-07-10 | 1985-07-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6213027U (en) |
-
1985
- 1985-07-10 JP JP10408585U patent/JPS6213027U/ja active Pending