JPS62130036A - Clock transmission type synchronizing data transmission system - Google Patents

Abstract

PURPOSE:To attain highly reliable data transmission by transmitting a data synchronizing clock together with a synchronizing data so as to facilitate the data transmission with a system not in a subsequent relation and to avoid data transmission error due to a slip. CONSTITUTION:A synchronizing data inputted from a data transmission system I to an interface circuit 20 is sampled at a data sampling circuit 1 by using a data synchronizing clock B of the system I. On the other hand, the clock b is subject to 1/2 frequency division and becomes a signal C. The signal C is sampled by a frequency f2 at a change point coding circuit 3 and when the signal C changes, a change point bit 1 is set. The output of the circuits 1, 3 in inputted to a data clock synthesis coding circuit 4, synchronizing data information sampled sequentially is inserted after the bit 1 and the result is sent as a transmission cod E via a transmission speed adjusting circuit 5. The transmission code E is recovered by an interface device 30, where a recovery data I and a data synchronizing clock H are generated and sent to a terminal equipment 40.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synchronous data transmission system between data transmission systems that are not in a subordinate synchronous relationship.

[Conventional technology]

Conventionally, in clock-synchronized data communication where clocks cannot be synchronized, that is, systems are independently synchronized without a dependent synchronization relationship, the received data is

Data is sampled using the received data synchronization clock from the other system, and data is transmitted using the own system's clock. That is, the transmission data synchronization clock for transmission data is generated using the own system's clock, and data is transmitted. For this reason, it is necessary to improve the frequency accuracy of the original oscillation circuit of each system and reduce the s')y'f' caused by one frequency difference.

[Problem that the invention seeks to solve]

By the way, in the conventional transmission method described above, for example, one data transmission/stem (bustem clock frequency iN, tQ
f which is the system clock frequency of f I) and the other data transmission system (/stem clock frequency 'Pf2)
Matching l and 12 perfectly often results in pick-pockets and de. Therefore, due to this slip and slip, there is a problem in that the transmitted data increases by one bit or is missing by one bit, making it impossible to perform normal data communication.

On the other hand, in order to reduce the severity of lag, it is necessary to increase the frequency accuracy of both system clocks.

However, increasing the frequency accuracy only makes the mechanism that generates the stem clock expensive, which is not only economically disadvantageous.

It becomes unreasonable in terms of cost.

[Failure to solve the problem] The clock transparent synchronous data transmission method of the present invention is as follows.

Data transmission without clock synchronization, i.e. independent synchronization/
tq' is used when data communication is performed by relaying the stem, and samples the 1/2 synchronous component of the clock for data transmission/stem at the frequency of the data transmission/stem transmission speed mentioned above, and encodes the change point information. A coding means, a coded data synchronization clock, a transmission means for transmitting the data synchronization clock for the evening change point information in accordance with the transmission speed of the sampler transmission t stem, and a transmission means for transmitting the data from the code transmitted in this way. separation means for separating synchronization clock information and synchronization data information; first regeneration means for regenerating a data synchronization clock from the separated data synchronization clock information; and said reproduced data synchronization clock. and second reproduction means for reproducing the synchronous data in synchronization with the synchronous data.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

First, referring to FIG. 1 which schematically shows an embodiment of the present invention, the data transmission system (1) and the data transmission/stem (2) operate independently of each other at /stem clock frequencies f and f2, respectively. Ori.

They are subordinate to each other and cannot synchronize. As shown in FIG. 3, the data transmission system is connected to a data transmission system (2) via an interface device 20, and the data transmission system (2) is further connected to a terminal device 40 by an interface device 30.

The synchronization data of the data transmission/stem (1) and the data synchronization clock are input to the interface device 20, and the synchronization data and the data synchronization clock are synthesized as described later (data→-clock).

The data is transmitted through the data transmission system (2), and the interface device 30 separates and reproduces synchronization data and a data synchronization clock from this composite signal, and inputs the separated signals to the terminal device 40.

Here, the interface device will be explained with reference also to FIGS. 2 to 4.

Circuit 3. Data/clock synthesis encoding circuit 4. Transmission speed adjustment circuit 5. Data sampling circuit 6° Clock waveform shaping circuit 7. Clock regeneration circuit 8゜Data/clock separation circuit 9. and a transmission speed adjustment circuit 10.

Synchronous data inputted to the interface circuit 20 from the data transmission system is sampled by the data sampling circuit 1 using the data synchronization clock (2) of the data transmission system (2). On the other hand, the frequency of 0.7 for 2 data synchronization is divided by ]/2 by the clock 1/2 frequency dividing circuit 2, and becomes a signal O having a 1/2 period component.

This 1/2 cycle component signal O is sampled at the frequency of the transmission speed of the data transmission system (■) by the change point encoding circuit 3 (sampling point ■), and the value of the 11 component signal O at 1/2 cycle II is “0” to “1” or “1” to “
0", i.e. from "0" to 1" or "
■When there is a change point from "" to "0", the bit "1" which is the change point information is set. Data sampling circuit]
The output of the data synchronization clock and the output of the changing point encoding circuit 3 are input to the data/clock synthesis encoding circuit 4, and the synchronous data information (D+ , D2, D3, etc.) are inserted, the encoding is completed, and the transmission rate adjustment circuit 5 adjusts the transmission rate to the transmission rate of the data transmission system (2) and transmits it as a transmission code (2).

This transmission code ■ is transmitted through the data transmission system [F] as shown in FIG. 1, and is reproduced by the interface device 30. The reception code 0 shown in Fig. 4 is the transmission rate adjustment circuit I.
The data is adjusted to the transmission speed of the terminal device 40 at step O, and separated into change point information of 1/2 period component and reproduced data information by the data clock separation circuit 9.

Ru. In the clock reproducing circuit 8, a 172-cycle component Q of the reproduced clock is generated based on the change point information of the 1/2-cycle component. This 1/2 period component 0 is doubled in frequency by the clock waveform shaping circuit 7, and the duty (outy) is
is set as 509g and reproduced as the data synchronization clock ■. On the other hand, the synchronized data information separated by the data/clock separation circuit 9 is synchronized with the data synchronization clock (2) and reproduced by the data/sun cylinder circuit 6, thereby becoming reproduced data.

Then, these data synchronization clock (1) and reproduction data are sent to the terminal device 40.

In this way, the synchronized data from the data transmission system and the clock for synchronizing the data are transmitted.

Since this synchronization data and the data synchronization clock are supplied to the last data receiving system (for example, a terminal device), as shown in Figure 5, there is virtually no data transmission system, and the data It can be assumed that the data synchronized directly from the transmission/system and the clock for data synchronization are connected to the final data receiving system (eg terminal equipment).

In addition, in the above embodiment, a case was explained in which two data transmission systems that cannot achieve subordinate synchronization with each other are provided, but if the above-mentioned interface device is placed between each data transmission system, three or more subordinate synchronizations can be achieved. Needless to say, the present invention can also be applied to cases where a data transmission system is provided that cannot be controlled.

〔Effect of the invention〕

As explained above, in the present invention, in the transmission of clock synchronized data, by transmitting the data synchronization clock together with the synchronization data, data transmission between systems that do not have a dependent relationship can be easily performed, and the frequency of the system clock can be easily transmitted. Data transmission errors caused by slips due to differences can be eliminated, and highly reliable data transmission can be provided.

[Brief explanation of drawings]

Fig. 1 is a system configuration diagram showing an outline of an embodiment of the present invention, Fig. 2 is a block diagram for explaining the functions of the interface device, and Fig. 3 is an explanation of encoding by the interface device shown in Fig. 2. FIG. 4 is a diagram for explaining decoding by the interface device shown in FIG. 2, and FIG. 5 is a system configuration diagram substantially equivalent to FIG. 1. l...Data sampling circuit, 2...Clock 1
/2 frequency divider circuit, 3... Change point encoding circuit, 4... Data/clock synthesis encoding circuit, 5... Transmission rate adjustment circuit. 6...Data sampling circuit, 7...Clock waveform shaping circuit, 8...Clock regeneration circuit, 9...Data/clock separation circuit, 10...Transmission speed adjustment circuit. 4'tJX 人(77s3) jl"F! I Ikeda Noriyasu 1st flash Figure 5-121)-5 (Ihon?n4-i;Nohiro-me;medi)
--, 9shi! Todogi Mimibiki: I≧3 every! to,(〕(
)Figure 3Figure 4

Claims (1)

[Claims] 1. A synchronous data transmission method used when data communication is performed by relaying an independent synchronous data transmission system, in which the synchronous component of 1/2 of the data synchronization clock is set to the frequency of the transmission speed of the data transmission system. an encoding means for sampling at and encoding the change point information, and including synchronization data sampled by the data synchronization clock in the encoded change point information of the data synchronization clock;
Separating the data synchronization clock information and synchronization data information from a transmission means that encodes and transmits the data in accordance with the transmission speed of the data transmission system, and a code containing the transmitted data synchronization clock information and synchronization data information. a separating means; a first reproducing means for reproducing a data synchronizing clock from the separated data synchronizing clock information; and reproducing synchronous data from the synchronous data information in synchronization with the reproduced data synchronizing clock. A clock-transparent synchronous data transmission system, characterized in that it comprises a second reproduction means.