JPS62128606A - Waveform equalizer - Google Patents

Waveform equalizer

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Publication number
JPS62128606A
JPS62128606A JP26855985A JP26855985A JPS62128606A JP S62128606 A JPS62128606 A JP S62128606A JP 26855985 A JP26855985 A JP 26855985A JP 26855985 A JP26855985 A JP 26855985A JP S62128606 A JPS62128606 A JP S62128606A
Authority
JP
Japan
Prior art keywords
input
output
waveform
delay line
resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26855985A
Other languages
Japanese (ja)
Inventor
Hironori Kitazawa
北沢 寛徳
Masayoshi Kamo
加茂 正義
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP26855985A priority Critical patent/JPS62128606A/en
Publication of JPS62128606A publication Critical patent/JPS62128606A/en
Pending legal-status Critical Current

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  • Digital Magnetic Recording (AREA)
  • Filters That Use Time-Delay Elements (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Abstract

PURPOSE:To reduce the interference between pulses by attenuating the amplitude at a part where an input pulse has a gentle slope to reduce the pulse width. CONSTITUTION:An input waveform is turned into a pulse E7 having its rear end part more gentle than the front end part at an input point 7. The delay time of a delay line 2 is demoted as TD then a waveform E9 which is delayed by the input E7 by a delay time TD and attenuated by an attenuator 4 is obtained at an inverse input 9 of a differential amplifier 6. Here no reflection is produced by a termination resistance 3 at the input 6 and the input E7 is obtained as it is at a non-inverse input 8 in the form of a waveform E8 containing no synthesized reflected wave. Then a waveform E10 is obtained at an output 10. This waveform E10 has its pulse width reduced compared with the input E7 and a form more approximate to a front-back symmetrical form in terms of a peak point. In such a way, the interference can be reduced between adjacent pulses.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、記憶装置の再生回路における波形等化器に
関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a waveform equalizer in a reproduction circuit of a storage device.

〔従来の技術〕[Conventional technology]

第5図は例えば日本通信技術@)の技術報告NK−67
59「磁気記録における再生波形修正」に示された記憶
装置の再生回路における従来の波形等化器のブロック図
であり、(1)は整合抵抗、(2)は遅延線、(4)は
減衰器、(6)は差動アンプである。(7)〜(9ンは
それぞれのブロックの入力点、ααは出力点である。
Figure 5 shows, for example, the technical report NK-67 of Japan Telecommunications Technology @).
59 "Reproduction Waveform Modification in Magnetic Recording" is a block diagram of a conventional waveform equalizer in a reproduction circuit of a storage device, in which (1) is a matching resistor, (2) is a delay line, and (4) is an attenuation. (6) is a differential amplifier. (7) to (9) are the input points of each block, and αα is the output point.

次に動作について、第5図の各部における波形を示す第
6図に従って説明する。因において、入力端())への
入力波形をE7とし、遅延線(2)の遅延時間をTDと
すると、差動アンプ(6)の非反転入力(8)ではE7
と、差動アンプ(6)の非反転入力(81で反射し、 
 E8より更に時間TDだけ遅延した反射波とが合成さ
れ、減衰器(4)で減衰された波形]11i9を差動ア
ンプ(6)の反転入力(9)で得る。すると、差動アン
プ(6)の出力(11では、  K7に対してパルス幅
の狭まった波形Ell)を得る。
Next, the operation will be explained with reference to FIG. 6, which shows waveforms at various parts in FIG. 5. In this case, if the input waveform to the input terminal () is E7 and the delay time of the delay line (2) is TD, then the non-inverting input (8) of the differential amplifier (6) is E7.
and the non-inverting input of the differential amplifier (6) (reflected at 81,
The reflected wave further delayed by time TD from E8 is combined and attenuated by the attenuator (4) to obtain a waveform]11i9 at the inverting input (9) of the differential amplifier (6). Then, the output of the differential amplifier (6) (in 11, a waveform Ell with a narrower pulse width than K7) is obtained.

このように、従来の等化器では、入カバルスの両縁部の
振幅を、遅延線(2)の遅延時間TD及び減衰器(4)
の減衰率で定まる度合で、パルスのピーク点に関して前
後対称に減衰させることによってパルス幅を狭めている
。従って、この波形等化器はE7のようなピーク点に関
して前後対称なパルスに対してならば、その対称性をそ
こなうことなくパルス幅を狭めることができ、隣接する
パルス相互の干渉を軽減することに有効でおる。
In this way, in the conventional equalizer, the amplitude of both edges of the input signal is calculated using the delay time TD of the delay line (2) and the attenuator (4).
The pulse width is narrowed by attenuating the pulse symmetrically with respect to the peak point of the pulse to a degree determined by the attenuation rate. Therefore, this waveform equalizer can narrow the pulse width without damaging the symmetry for pulses that are symmetrical about the peak point, such as E7, and reduce mutual interference between adjacent pulses. It is effective.

〔発明が解決しようとする問題点〕 従来の波形等化器は以上のよ5に構成されているので、
入力波形としてはピーク点に関して前後対称であること
が必要であり、非対称波形を扱うKは不適当である事、
又はその非対称性をかえって助長する事のため、隣接す
るパルス相互の干渉を軽減するという効果が得られない
という問題点があった。
[Problems to be solved by the invention] Since the conventional waveform equalizer is configured as shown in 5 above,
The input waveform must be symmetrical with respect to the peak point, and K is inappropriate for handling asymmetrical waveforms.
Alternatively, since the asymmetry is exacerbated, there is a problem in that the effect of reducing mutual interference between adjacent pulses cannot be obtained.

この発明は上記のような問題点を解消するためになされ
たもので、入力波形として前後非対称なパルスを扱う場
合に、それをできるだけ対称に近くするとともにパルス
幅も狭め、隣接パルスの相互干渉を軽減することができ
2等化効果の高い波形等化器を得ることを目的とする。
This invention was made to solve the above-mentioned problems, and when dealing with front-back asymmetrical pulses as input waveforms, it is possible to make them as symmetrical as possible, narrow the pulse width, and prevent mutual interference between adjacent pulses. It is an object of the present invention to obtain a waveform equalizer that can reduce the amount of noise and has a high 2-equalization effect.

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係る波形等化器は整合された入力信号を所定
時間遅延させろ遅延線と、この遅延線の出力信号または
瞥合入力信号のいずれかを所定割合で減衰する減衰器と
、この減衰器の出力信号と上記遅延線の出力信号または
整合された入力信号のうちで減衰器に入力されない力の
信号をペアリング抵抗を介して入力しアナログ演算する
差動アンプを備えるとともに、上記遅延線を終端する終
端抵抗を設けたものである。
The waveform equalizer according to the present invention includes a delay line that delays a matched input signal for a predetermined time, an attenuator that attenuates either the output signal of the delay line or the input signal at a predetermined rate, and the attenuator. and a differential amplifier that inputs the output signal of the delay line or the force signal that is not input to the attenuator among the matched input signals through a pairing resistor and performs analog calculation, and the delay line A terminating resistor is provided to terminate the line.

〔作用〕[Effect]

この発明における減衰器は遅延線の出力信号または整合
された入力信号を所定割合で減衰し、差動アンプはこの
減衰されf、、信号と1時間的にずれている減衰されな
い信号とでアナログ演算するのでピーク点に関して前後
非対称な波形の入カバルスに対し、傾斜のなだらかな部
分の振幅を減衰させることにより、出力パルスを対称形
に近づけるとともにパルス幅も狭まる作用が有する。ま
た終端抵抗は差動アンプからの反射波を防止している。
The attenuator in this invention attenuates the output signal of the delay line or the matched input signal at a predetermined rate, and the differential amplifier performs an analog calculation using the attenuated signal f, and the unattenuated signal shifted by one time. Therefore, for an input pulse whose waveform is asymmetrical with respect to the peak point, by attenuating the amplitude of the part with a gentle slope, the output pulse can be made closer to a symmetrical shape and the pulse width can be narrowed. The terminating resistor also prevents reflected waves from the differential amplifier.

〔発明の実施例〕[Embodiments of the invention]

以下、この発明の一実施例を囚について説明する。第1
図はこの発明の一実施例のブロック図である。この図に
おいて、入力信号(7)は整合抵抗(1)で受けられ、
この出力はペアリング抵抗(5)及び遅延線(21に分
岐する。ペアリング抵抗(5)の出力は差動アンプ(6
)の非反転入力に接がれている。−力。
An embodiment of the present invention will be described below regarding a prisoner. 1st
The figure is a block diagram of an embodiment of the present invention. In this figure, an input signal (7) is received by a matching resistor (1);
This output is branched to a pairing resistor (5) and a delay line (21. The output of the pairing resistor (5) is branched to a differential amplifier (6).
) is connected to the non-inverting input of -Power.

遅延線(2)の出力に1終端抵抗(3)により終端され
ている。更に遅延線(2)の中間タップは減衰器(4)
を経て差動アンプ(6)の反転入力に導ひかれている。
The output of the delay line (2) is terminated by a single terminating resistor (3). Furthermore, the intermediate tap of the delay line (2) is an attenuator (4).
and is led to the inverting input of the differential amplifier (6).

差動アンプ(6)の出力からその入力に対応する出力信
号a1を得ることができる。
An output signal a1 corresponding to the input of the differential amplifier (6) can be obtained from the output of the differential amplifier (6).

なお、終端抵抗(3)は遅延線(2)の特性インピーダ
ンス値と等しい値をもって、遅延線を終端し、信号の反
射を防ぎ、ペアリング抵抗(5)ハ減衰器(4)の直列
抵抗値と等しい値をもって減衰器(4:とのペアリング
をとるものである。
Note that the terminating resistor (3) has a value equal to the characteristic impedance value of the delay line (2), and terminates the delay line to prevent signal reflection. It is paired with the attenuator (4:) with a value equal to .

次罠動作について説明する。第2図は第1−の各部の波
形を示す。図において入力点(7)での入力波形をE7
のような後縁部の傾斜が前縁部に比してなだらかなパル
スとし、遅延線(2)の遅延時間をTDとすると、差動
アンプ(6)の反転入力(9)では。
Next, I will explain the trap operation. FIG. 2 shows the waveforms of each part of 1-. In the figure, the input waveform at input point (7) is E7
If the slope of the trailing edge is gentler than that of the leading edge, and the delay time of the delay line (2) is TD, then at the inverting input (9) of the differential amplifier (6).

IC7より時間TDだげ遅延し減衰器(4)で減衰され
た波形E9を得る。
A waveform E9 is obtained which is delayed by the time TD from IC7 and attenuated by the attenuator (4).

また、終端抵抗(3)Kより差動アンプ(6)の反転入
力(9)で反射は起こらず、非反転入力(8)では入力
E7を反射波の合成されない波形E8としてそのまま得
る。そして、出力OQではE7に比してパルス幅が挟ま
り、ピーク点に関して前後対称形に近づいた波形IJo
を得る。
Furthermore, no reflection occurs at the inverting input (9) of the differential amplifier (6) due to the termination resistor (3) K, and the input E7 is obtained as it is as a waveform E8 in which reflected waves are not synthesized at the non-inverting input (8). In the output OQ, the pulse width is narrower than that of E7, and the waveform IJo is close to being symmetrical with respect to the peak point.
get.

このように、この発明の等化量では遅延ffM (z)
の遅延時間Tl)及び減衰器(4)の減衰率で定まる度
合で、パルスの後縁部の振幅を減衰させることによって
パルス幅を狭めている。従って、この等化量は、E7の
ような後縁部の傾斜が前縁部に比してなだらかな入力パ
ルスに対して、それを対称形に近づけるとともにパルス
幅を狭めることができ。
In this way, with the equalization amount of this invention, the delay ffM (z)
The pulse width is narrowed by attenuating the amplitude of the trailing edge of the pulse to a degree determined by the delay time Tl) and the attenuation rate of the attenuator (4). Therefore, this equalization amount can make an input pulse, such as E7, whose trailing edge has a gentler slope than the leading edge, become more symmetrical and narrow the pulse width.

隣接するパルス相互の干渉を軽減するのに有効である。This is effective in reducing mutual interference between adjacent pulses.

なお、上記実施例では入力パルスとして後縁部の傾斜が
前縁部に比してなだらかなものを扱ったが、前縁部の傾
斜が後縁部に比してなだらかなものについて第3図の実
施例を参照して説明する。
In the above embodiment, the input pulse was treated as an input pulse in which the slope of the trailing edge was gentler than that of the leading edge, but FIG. This will be explained with reference to an example.

第3図において、整合抵抗(1)からの出力は減衰器(
4)及び遅延i (21K分岐し、減衰器(4)の出力
が差動アンプ(6)の反転入力に、遅延線(2)の中間
タップからペアリング抵抗(5)ヲ経て差動アンプ(6
)の非反転入力に入力されるものである。
In Figure 3, the output from the matching resistor (1) is the attenuator (
4) and delay i (21K branched, and the output of the attenuator (4) is connected to the inverting input of the differential amplifier (6) from the intermediate tap of the delay line (2) through the pairing resistor (5) to the differential amplifier ( 6
) is input to the non-inverting input.

第4図は第3図の各部の波形を示す。すなわちなお図中
同一記号は同−又は相当部分を示す。
FIG. 4 shows waveforms at various parts in FIG. That is, the same symbols in the figures indicate the same or equivalent parts.

入力波形がE7とすると、差動アンプ(6)の非反転入
力(8)での波形がE8その反転入力(9)でのものが
E9.出力α@でのものが]lJoとなる。
If the input waveform is E7, the waveform at the non-inverting input (8) of the differential amplifier (6) is E8, and the waveform at the inverting input (9) is E9. The output α@ becomes ]lJo.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば、入力パルスの傾斜が
なだらかな部分の振幅を減衰させることによってパルス
幅を狭くしたので2前後非対称な入力パルスを扱う場合
、それをピーク点に関して前後対称な形に近づけながら
パルス幅を狭くして隣接するパルス相互の干渉を軽減す
る効果がある。
As described above, according to the present invention, the pulse width is narrowed by attenuating the amplitude of the part where the slope of the input pulse is gentle. This has the effect of reducing interference between adjacent pulses by narrowing the pulse width while approaching the shape.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例のブロック図、第2図は第
1図の各部の波形を示す図、第3図はこの発明の他の実
施例のブロック図、第4図は第3図の各部の波形を示す
図、第5図は従来の波形等化器のブロック図、第6図は
第5図の各部の波形を示す図である。 図において、(1)は整合抵抗、(2)は遅延線、(3
)は終端抵抗、(41は減衰器、(5)はペアリング抵
抗、(6)は差動アンプ。 第1図
FIG. 1 is a block diagram of one embodiment of this invention, FIG. 2 is a diagram showing waveforms of each part of FIG. 1, FIG. 3 is a block diagram of another embodiment of this invention, and FIG. FIG. 5 is a block diagram of a conventional waveform equalizer, and FIG. 6 is a diagram showing waveforms of each part in FIG. 5. In the figure, (1) is a matching resistor, (2) is a delay line, and (3
) is the termination resistor, (41 is the attenuator, (5) is the pairing resistor, and (6) is the differential amplifier.

Claims (3)

【特許請求の範囲】[Claims] (1)入力信号を整合抵抗によつて整合して入力し、所
定時間遅延する遅延線と、この遅延線の特性インピーダ
ンス値と等しい値をもつて遅延線を終端する終端抵抗と
、上記整合抵抗の出力振幅、または上記遅延線の出力振
幅のいずれかを入力し所定割合で減衰する減衰器と、上
記整合抵抗の出力または上記遅延線の出力で、かつこの
減衰器の非入力側出力を入力とし、この減衰器の直列抵
抗値と等しい値をもつて、この減衰器とのペアリングを
とるペアリング抵抗と、このペアリング抵抗の出力を非
反転入力とし、上記減衰器の出力を反転入力としてアナ
ログ演算し、その結果を出力する差動アンプとを備えた
ことを特徴とする波形等化器。
(1) A delay line that matches and inputs an input signal using a matching resistor and delays it for a predetermined time, a terminating resistor that terminates the delay line with a value equal to the characteristic impedance value of this delay line, and the matching resistor. or the output amplitude of the delay line and attenuates it at a predetermined rate, and the output of the matching resistor or the output of the delay line, and the non-input side output of this attenuator is input. and a pairing resistor that pairs with this attenuator with a value equal to the series resistance value of this attenuator, the output of this pairing resistor as a non-inverting input, and the output of the above attenuator as an inverting input. 1. A waveform equalizer comprising: a differential amplifier that performs analog calculations and outputs the results.
(2)減衰器は遅延線の出力を入力し、所定割合で減衰
し、ペアリング抵抗は整合抵抗からの出力を入力するこ
とを特徴とする特許請求の範囲第1項記載の波形等化器
(2) The waveform equalizer according to claim 1, wherein the attenuator inputs the output of the delay line and attenuates it at a predetermined rate, and the pairing resistor inputs the output from the matching resistor. .
(3)減衰器は整合抵抗の出力を入力して、所定割合で
減衰し、ペアリング抵抗は遅延線の出力を入力すること
を特徴とする特許請求の範囲第1項記載の波形等化器。
(3) The waveform equalizer according to claim 1, wherein the attenuator inputs the output of the matching resistor and attenuates it at a predetermined rate, and the pairing resistor inputs the output of the delay line. .
JP26855985A 1985-11-29 1985-11-29 Waveform equalizer Pending JPS62128606A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26855985A JPS62128606A (en) 1985-11-29 1985-11-29 Waveform equalizer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26855985A JPS62128606A (en) 1985-11-29 1985-11-29 Waveform equalizer

Publications (1)

Publication Number Publication Date
JPS62128606A true JPS62128606A (en) 1987-06-10

Family

ID=17460209

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26855985A Pending JPS62128606A (en) 1985-11-29 1985-11-29 Waveform equalizer

Country Status (1)

Country Link
JP (1) JPS62128606A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5612145A (en) * 1991-11-14 1997-03-18 Victor Company Of Japan, Ltd. Perpendicular magnetic medium and manufacturing method for the medium

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5612145A (en) * 1991-11-14 1997-03-18 Victor Company Of Japan, Ltd. Perpendicular magnetic medium and manufacturing method for the medium

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