JPS62128607A - Waveform equalizing circuit - Google Patents

Waveform equalizing circuit

Info

Publication number
JPS62128607A
JPS62128607A JP26856185A JP26856185A JPS62128607A JP S62128607 A JPS62128607 A JP S62128607A JP 26856185 A JP26856185 A JP 26856185A JP 26856185 A JP26856185 A JP 26856185A JP S62128607 A JPS62128607 A JP S62128607A
Authority
JP
Japan
Prior art keywords
waveform equalization
differential
signal
waveform
differential amplifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP26856185A
Other languages
Japanese (ja)
Other versions
JPH0328085B2 (en
Inventor
Keiichi Nishikawa
啓一 西川
Masayoshi Kamo
加茂 正義
Hajime Sasaki
肇 佐々木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP26856185A priority Critical patent/JPS62128607A/en
Publication of JPS62128607A publication Critical patent/JPS62128607A/en
Publication of JPH0328085B2 publication Critical patent/JPH0328085B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE:To reduce the peak shift as well as the effects of external noises by shaping the waveform read out of a magnetic head and reducing the half value width. CONSTITUTION:A differential amplifier 1 has a very large input impedance and a delay line 2 has a delay amount taud connected to the differential input terminal of a differential amplifier 1 via the 1st and 2nd resistances Rb used for setting the waveform equalization factor K. A signal source 3 is connected to a positive input terminal (a) of the amplifier 1 via the 3rd resistances Ra used for setting the factor K. Then a signal source 4 is connected to a negative input terminal (b) of the amplifier 1 via the 4th resistance Ra used for setting the factor K. Both sources 3 and 4 deliver the differential signals. Here the 5th and 6th resistances Rc are matched with the characteristic impedance R0 of the line 2 together with the 3rd/4th and 1st/2nd resistances Ra and Rb respectively and therefore earths to both ends of the line 2.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は磁気記録装置の読出し回路に含まれる波形等
化回路に関するもので、磁気ヘッドから読み出される波
形を整形し2品質を高めるために適用するものである。
[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a waveform equalization circuit included in a readout circuit of a magnetic recording device, and is applied to shape the waveform read from a magnetic head and improve the quality. It is something to do.

〔従来の技術〕[Conventional technology]

磁気ディスク装置において磁気記録の高密度化を図る場
合、読出し信号の波形相互の干渉によシミ圧しベル低下
やパターンピークシフトが発生し。
When attempting to increase the density of magnetic recording in a magnetic disk device, interference between the waveforms of read signals causes stain pressure, lowering of the signal level, and pattern peak shift.

信号検出の性能が低下する。このため、読出し回路に波
形等化回路を適用し、読出し波形の半値幅を狭くして波
形間の相互干渉を少なくして、前記電圧レベル低下およ
びパターンピークシフトを軽減させる手段が用いられて
いる。
Signal detection performance is degraded. For this reason, a waveform equalization circuit is applied to the readout circuit to narrow the half-width of the readout waveform to reduce mutual interference between waveforms, thereby reducing the voltage level drop and pattern peak shift. .

第3図は2例えば2日本通信技術(株)の技術報告NK
−6759r磁気記録における再生波形修正」の中で詳
述されている従来の遅延線を用いた波形等化回路の一実
施例である。図において、(1)は入力インピーダンス
が非常に大きな差動増幅器であfi、(2)は遅延量τ
d、特性インピーダンス几0を持つ遅延線であ!0.(
31は磁気ヘッドの読出し信号源を等制約に表わしたも
のであり、Ra、几brRcは抵抗である。ここで”b
+ ”cは波形等化率Kを決定するものであシ、さらに
”a+ ”b+ RCの組合せで遅延線の特性インピー
ダンスRQと整合をとる。
Figure 3 shows 2For example, 2Japan Communication Technology Co., Ltd.'s technical report NK.
This is an example of a waveform equalization circuit using a conventional delay line, which is detailed in ``Reproduction Waveform Modification in Magnetic Recording'', 6759r. In the figure, (1) is a differential amplifier with very large input impedance fi, and (2) is the delay amount τ
d is a delay line with characteristic impedance 0! 0. (
31 represents the read signal source of the magnetic head with equal constraints, and Ra and Rc are resistances. Here “b”
+ ``c'' determines the waveform equalization rate K, and the combination of ``a+''b+ RC matches the characteristic impedance RQ of the delay line.

次に動作について説明する。Next, the operation will be explained.

信号線(3)よシ孤立波n(t、)が入力された場合を
考える。このときE(()として逆正接関数の微分形を
仮定する。
Consider the case where a solitary wave n(t,) is input through the signal line (3). At this time, a differential form of the arctangent function is assumed as E(().

この信号B(i)が入力された場合、遅延線(2)の整
合端(1)には なる電圧が発生する。
When this signal B(i) is input, a voltage is generated at the matching end (1) of the delay line (2).

この整合端に発生した電圧は抵抗線とR8によ多分割さ
れ差動増幅器(1)の負の入力端にはなる電圧が入力さ
れる。
The voltage generated at this matching terminal is divided into multiple parts by the resistance line and R8, and the voltage is inputted to the negative input terminal of the differential amplifier (1).

一方、遅延線の反射端(b)は特性インピーダンスで整
合されておらず、この場合整合端(a)よシ入力された
信号は遅延時間τdだけ遅れて反射端(b)で全反射し
、その時反射端には整合端(a)よ)入力された信号電
圧の2倍の電圧が発生する。
On the other hand, the reflection end (b) of the delay line is not matched by characteristic impedance, and in this case, the signal input from the matching end (a) is totally reflected at the reflection end (b) after a delay time τd. At that time, a voltage twice as high as the input signal voltage (from the matching end (a)) is generated at the reflection end.

信号源(3)より E(t)なる信号を入力した場合2
反射端(b)には なる電圧が発生する。
When inputting a signal E(t) from signal source (3) 2
A voltage is generated at the reflective end (b).

よって、差動増幅器の出力は とおくと。Therefore, the output of the differential amplifier is And then.

となる。becomes.

ここで、あらためてt−τdをtとおきなおすと。Here, if we replace t-τd with t.

この波形等化回路は原波形信号から時間τdだけ遅れた
信号と進んだ信号の和を波形等化率に倍し。
This waveform equalization circuit multiplies the sum of a signal delayed by a time τd and a signal advanced from the original waveform signal to the waveform equalization rate.

両者の差を出力することになる。この波形等化による効
果を示したのが第4図であシ、(イ)は半値幅W50な
る入力孤立波形、(ロ)はそれに対し時間τdだけ進め
、波形等化率に倍した信号並びに時間τdだけ遅らせ、
波形等化率に倍した信号を示す。(ハ)は波形等化後の
孤立波であ91図のように等死後の半値幅は等化前に比
べ狭くなっている。
The difference between the two will be output. Figure 4 shows the effect of this waveform equalization, in which (a) is an input isolated waveform with a half-width W50, (b) is a signal that is advanced by time τd and multiplied by the waveform equalization rate, and Delayed by time τd,
Shows the signal multiplied by the waveform equalization rate. (C) is a solitary wave after waveform equalization, and as shown in Fig. 91, the half-width after iso-death is narrower than before equalization.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

一般に磁気ディスク装置は信号対雑音比の確保のため、
信号処理回路の入力、出力は差動の形体で構成すること
が多い。しかし、従来の波形等化回路は第3図で示した
ごとく、入力が差動で構成されておらず、この部分で差
動系をくずすことになシ、外来雑音に対し信号対雑音比
の悪化を招くことになる。
In general, magnetic disk drives use
Inputs and outputs of signal processing circuits are often configured in a differential manner. However, as shown in Figure 3, the conventional waveform equalization circuit does not have a differential input, so it is difficult to destroy the differential system in this part, and the signal-to-noise ratio is low against external noise. This will lead to deterioration.

この発明は上記のような問題点を解消するためになされ
たもので、差動入力のまま波形等化を施し、ピークシフ
トを軽減する回路を得ることを目的とする。
The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a circuit that performs waveform equalization on differential inputs and reduces peak shifts.

〔問題点を解決するだめの手段〕[Failure to solve the problem]

この発明に係る磁気ディスク装置の波形等化回路は、差
動増幅器の正負2つの入力端子間に抵抗を介して遅延線
を接続し、また、波形等化回路に入力する差動信号波形
は抵抗を介して差動増幅器の正負入力端子に接続したも
のである。
In the waveform equalization circuit of the magnetic disk device according to the present invention, a delay line is connected between the positive and negative input terminals of a differential amplifier via a resistor, and the differential signal waveform input to the waveform equalization circuit is It is connected to the positive and negative input terminals of the differential amplifier via the terminal.

〔作用〕[Effect]

この発明における波形等化回路は、入力、出力とも差動
の形体をとシ、波形等化、増幅され、信号対雑音比を悪
化させることなく、ピークシフトを軽減させることがで
きる。
The waveform equalization circuit according to the present invention has a differential configuration for both input and output, and the waveform is equalized and amplified, so that peak shift can be reduced without deteriorating the signal-to-noise ratio.

〔発明の実施例〕[Embodiments of the invention]

以下、この発明の一実施例を図について説明する。この
波形等化回路は入力信号Ft(t、)からそれを波形等
化率に倍し、さらに遅延量τdだけ遅れた信号を差し引
くことによ多波形等化を行うものである。
An embodiment of the present invention will be described below with reference to the drawings. This waveform equalization circuit performs multi-waveform equalization by multiplying the input signal Ft(t,) by a waveform equalization rate and further subtracting a signal delayed by the delay amount τd.

第1図において、(1)は入力インピーダンスが非常に
大きい差動増幅器であり、(2)は差動増幅器(1)の
差動入力端にそれぞれ波形等化率にの設定のだめの第1
.第2の抵抗線を介して接続された遅延量τdを持つ遅
延線であL(31は差動増幅器(1)の正入力端子(a
)に波形等化率にの設定のための第3の抵抗へを介して
接続された信号源であ、り、(41は差動増幅器(1)
の負入力端子(1))に波形等化率にの設定のための第
40蝋抗Raを介して接続され、信号源(3)とともに
差動信号を出力する信号源である。
In Figure 1, (1) is a differential amplifier with a very large input impedance, and (2) is a first set of waveform equalization ratio settings at the differential input terminal of differential amplifier (1).
.. L (31 is the positive input terminal (a) of the differential amplifier (1)
) is a signal source connected to a third resistor for setting the waveform equalization rate, and (41 is a differential amplifier (1)
It is a signal source that is connected to the negative input terminal (1) of the signal generator (1) via the 40th wire resistor Ra for setting the waveform equalization rate, and outputs a differential signal together with the signal source (3).

また、都は第3.第4および第1.第2の抵抗〜+ ”
bとともに遅延線(2)の特性インピーダンスPL(、
と整合するため、遅延線のそれぞれの両端と接地する第
5.第6の抵抗である。
Also, the capital is the third. Fourth and first. Second resistance~+”
b and the characteristic impedance PL of the delay line (2) (,
A fifth . This is the sixth resistance.

このとき遅延線(2)の特性インピーダンス几0は各抵
抗によって整合されておシ、信号源(3) 、 (41
の出力インピーダンスが非常に小さく、かつ差動増幅器
(1)の入力インピーダンスが非常に大きいとして。
At this time, the characteristic impedance 0 of the delay line (2) is matched by each resistor, and the signal source (3), (41
Suppose that the output impedance of the differential amplifier (1) is very small, and the input impedance of the differential amplifier (1) is very large.

が整合条件となる。is the consistency condition.

次にこの波形等化回路の動作について説明する。Next, the operation of this waveform equalization circuit will be explained.

信号源(3)と(4)から孤立波としてそれぞれE(t
)と−E(t)が入力されていると仮定する。この時、
差動増幅器(11の入力端(a)には KoFi(t)  KI B(t−τd)なる電圧が発
生する。ここで である。なお、ここでKOFl(t)を第2図(イ)に
、KIB(を−τd)を同図(ロ)に、KoE(t)−
に1B(を−τd)を同図(ハ)に示す。また差動増幅
器(1)のもう一方の入力端(bJにも、この電圧の逆
極性の電圧が発生する。
E(t
) and −E(t) are input. At this time,
A voltage KoFi(t) KI B(t-τd) is generated at the input terminal (a) of the differential amplifier (11). In this figure, KIB(-τd) is shown in the same figure (b), and KoE(t)-
1B (-τd) is shown in the same figure (c). Further, a voltage of opposite polarity to this voltage is also generated at the other input terminal (bJ) of the differential amplifier (1).

このとき波形等化率には で表わすことができる。At this time, the waveform equalization rate is It can be expressed as

すなわち、この波形等化回路は孤立波g(t、)に対し
て、その波形を波形等化率に倍し、さらに遅延量τdだ
け遅らせた信号を差し引くことによシ可能となる。
That is, this waveform equalization circuit can operate on the isolated wave g(t,) by multiplying the waveform by the waveform equalization rate and further subtracting a signal delayed by the delay amount τd.

このように上記実施例によれば、差動増幅器の正負入力
端子に、それぞれ抵抗を介して差動信号を入力すると共
に、この入力信号を分圧抵抗によシ減衰させ、遅延線を
介して差動増幅器の各々相手側端子に供給しているので
、半値幅W50を狭くすることができ、かつ外来雑音の
影響も軽減しうるものである。
In this way, according to the above embodiment, a differential signal is input to the positive and negative input terminals of the differential amplifier through the respective resistors, and this input signal is attenuated by the voltage dividing resistor, and is then input through the delay line. Since the signal is supplied to each other terminal of the differential amplifier, the half width W50 can be narrowed, and the influence of external noise can also be reduced.

なお、この波形等化回路の説明においては、第2図のよ
うな対称な孤立波を入力した場合の例について示したが
1例えば記録媒体や磁気ヘッドの条件によっては孤立波
そのものが対称でない場合もある。例えば図5に示す孤
立波の場合にも、この波形等化回路を適用することによ
シ、半値幅W50を狭くすることが可能となる。
In the explanation of this waveform equalization circuit, we have shown an example where a symmetrical solitary wave is input as shown in Figure 2.1 For example, depending on the conditions of the recording medium or magnetic head, the solitary wave itself may not be symmetrical. There is also. For example, even in the case of the solitary wave shown in FIG. 5, by applying this waveform equalization circuit, it is possible to narrow the half-width W50.

〔発明の効果〕〔Effect of the invention〕

以上のように本発明に係る波形等化回路によれば、磁気
ヘッドから読み出される波形を整形し。
As described above, the waveform equalization circuit according to the present invention shapes the waveform read from the magnetic head.

半値幅W50を小さくすることによって、ピークシ(Q
) フトを軽減でき、同時に外来雑音の影響も軽減できるた
め、信頼性の高い読み出し回路を実現することができる
By reducing the half width W50, the peak shift (Q
) It is possible to reduce the noise and at the same time reduce the influence of external noise, making it possible to realize a highly reliable readout circuit.

【図面の簡単な説明】 第1図はこの発明の一実施例による波形等化回路の回路
図、第2図はこの発明による波形等化の原理を模した図
、第3図は従来の波形等化回路の回路図、第4図は従来
の波形等化の原理を模した図、第5図はこの発明による
他の波形等化の原理を模した図である。 図中、(1)は差動増幅器、(2)は遅延線、(3)は
信号源、〜は第3.第4の抵抗、FLbは第1.第2の
抵抗、几。は第5.第6の抵抗である。 なお2図中同一符号は同一または相当部分を示すものと
する。
[Brief Description of the Drawings] Figure 1 is a circuit diagram of a waveform equalization circuit according to an embodiment of the present invention, Figure 2 is a diagram simulating the principle of waveform equalization according to the present invention, and Figure 3 is a diagram of a conventional waveform equalization circuit. The circuit diagram of the equalization circuit, FIG. 4 is a diagram simulating the principle of conventional waveform equalization, and FIG. 5 is a diagram simulating the principle of another waveform equalization according to the present invention. In the figure, (1) is a differential amplifier, (2) is a delay line, (3) is a signal source, and ~ is a third . The fourth resistor, FLb, is the first resistor. The second resistance, Rin. is the fifth. This is the sixth resistance. Note that the same reference numerals in the two figures indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims] 磁気記録装置の信号読出し回路に含まれる波形等化回路
において、差動増幅器の正負2つの入力端子に第1、第
2の抵抗を接続し、前記第1、第2の抵抗の他の端子は
2つの接続端子を持つ遅延線にそれぞれ接続され、また
、差動入力信号のそれぞれ正負極性信号は第3、第4の
抵抗を介して前記差動増幅器の正負2つの入力端子と接
続され、さらに前記遅延線の2つの接続端子には第5、
第6の抵抗が接続され、他方を接地する回路接続からな
り、前記遅延線の特性インピーダンスとの整合は第1、
第2、第3、第4、第5、第6の抵抗の組合せで行うこ
とを特徴とする波形等化回路。
In a waveform equalization circuit included in a signal readout circuit of a magnetic recording device, first and second resistors are connected to two positive and negative input terminals of a differential amplifier, and the other terminals of the first and second resistors are Each of the differential input signals is connected to a delay line having two connection terminals, and each of the positive and negative polarity signals of the differential input signal is connected to the two positive and negative input terminals of the differential amplifier via a third and fourth resistor. The two connection terminals of the delay line have a fifth,
A sixth resistor is connected and the other is grounded, and the matching with the characteristic impedance of the delay line is determined by the first,
A waveform equalization circuit characterized in that it is implemented by a combination of second, third, fourth, fifth, and sixth resistors.
JP26856185A 1985-11-29 1985-11-29 Waveform equalizing circuit Granted JPS62128607A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26856185A JPS62128607A (en) 1985-11-29 1985-11-29 Waveform equalizing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26856185A JPS62128607A (en) 1985-11-29 1985-11-29 Waveform equalizing circuit

Publications (2)

Publication Number Publication Date
JPS62128607A true JPS62128607A (en) 1987-06-10
JPH0328085B2 JPH0328085B2 (en) 1991-04-18

Family

ID=17460236

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26856185A Granted JPS62128607A (en) 1985-11-29 1985-11-29 Waveform equalizing circuit

Country Status (1)

Country Link
JP (1) JPS62128607A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56154815A (en) * 1980-04-09 1981-11-30 Sperry Rand Corp Delay line spectrum shaping differentiating circuit with signal detecting balanced tap

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56154815A (en) * 1980-04-09 1981-11-30 Sperry Rand Corp Delay line spectrum shaping differentiating circuit with signal detecting balanced tap

Also Published As

Publication number Publication date
JPH0328085B2 (en) 1991-04-18

Similar Documents

Publication Publication Date Title
JPS6243267B2 (en)
US4346412A (en) Read signal processing circuit
US3775759A (en) Magnetic recording and readback systems with raised cosine equalization
US4757395A (en) Waveform equalizing circuit
JPS62231404A (en) Waveform equalizing device
JPS62128607A (en) Waveform equalizing circuit
US4806792A (en) Differential amplifier circuit
US4591939A (en) Waveform equivalent circuit
US5249086A (en) H.D.A. pulse shaping system using a differential delay line with multiple inputs
JPS6199906A (en) Waveform equalizing circuit
JPS63114423A (en) Data demodulation method
JPS58129839A (en) Delay line phase and amplitude equalizer
JP2511847B2 (en) Waveform equalization circuit
JP2638219B2 (en) Magnetic recording / reproducing circuit
JP2845878B2 (en) Recording / reproducing method of digital synchronization signal
JPS58182115A (en) Waveform equalizing circuit
JPS63195809A (en) Reading circuit for magnetic recorder
JP2522028B2 (en) Perpendicular magnetic recording / reproduction equalization method
JPS6050673A (en) Signal detecting circuit
JPS6243805A (en) Vertical magnetic recording and reproducing equalization system
JPS5829914B2 (en) Single point emphasis circuit
JPS62256202A (en) Readout circuit for magnetic disk device
JPS60137116A (en) Waveform equalizer
JPH01176302A (en) Waveform equalizing circuit for recording and reproducing device
JPS60175257A (en) Reading circuit