JPS63195809A - Reading circuit for magnetic recorder - Google Patents

Abstract

PURPOSE:To simultaneously improve a phase margine and a slice level margine based on a reading signal from a magnetic head by connecting waveform equalizing circuits having respectively different attenuation factors to the prestages of a limiter circuit and a gate generating circuit. CONSTITUTION:A reading signal from a magnetic head is respectively applied to the waveform equalizing circuits 11, 15 and the signal equalized by the circuit 11 is differentiated by a differentiation circuit 12 so that a peak position is converted into a zero crossing point of a differentiated waveform and the output of the circuit is discriminated by a data discriminating circuit 17 through a low-pass filter 13 and a limiter circuit 14. On the other hand, the equalized signal from the circuit 15 is inputted to a gate generating circuit 16 through a low-pass filter 13 and sent to the circuit 17. In this case, the waveform equalizing effects of the circuits 11, 15 are different from each other and the attenuation factors are also different. In a phase margine system based on the waveform equalizing circuits, the attenuation factors are set up so that the sum of an S/N jitter value and a pattern peak shifting value is minimized. In a slice level margine system, the attenuation factors are set up so that the sum of voltage dropping rates due to S/N ratios is minimized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a readout circuit for a magnetic recording device, and particularly to a readout circuit for a magnetic recording device suitable for improving recording and reproducing characteristics.

[Conventional technology]

In magnetic recording devices such as magnetic disk drives, in order to cope with higher recording densities, a method is used to improve recording and reproducing characteristics isometrically by processing the waveform read by a magnetic head in a reproducing circuit. .

One of these methods is the method described in Japanese Unexamined Patent Publication No. 58-182114.
A waveform equalization circuit consisting of a combination of a delay line, an attenuator, and a differential amplifier as shown in the figure is known. However, if the circuit constants of the delay time and the attenuation rate are fixed, the effect of equalization, that is, the amount of reduction in pattern peak shift, is constant, and the degree of equalization is either too much or too little.

Therefore, recently, a method has been proposed to reduce the influence on the pattern peak shift due to the difference in characteristics of readout waveforms. As an example of this, for example, the above-mentioned Japanese Patent Application Laid-open No. 5
There is No. 8-182114.

This is done by switching the delay time, attenuation rate, and other circuit constants according to the characteristics of the readout waveform to narrow the waveform before and after its peak, prevent waveform undershoot, and reduce over- or under-equalization. It is something to do. An example of a readout circuit of a magnetic recording device including such a waveform equalization circuit is shown in FIG.

In FIG. 2, for example, a read signal from a magnetic head is waveform-equalized by a waveform equalization circuit 1, and then a differential circuit 2 converts the peak position to a zero-crossing point of the differential waveform, and then a low-pass filter 3. The data passes through the limiter circuit 4 and is subjected to data discrimination by the data discrimination circuit 6. The timing of this data discrimination is determined by filtering the waveform equalized signal by the low-pass filter 3, inputting it to the gate generation circuit 5, and applying the obtained gate pulse to the data discrimination circuit 6.

[Problem that the invention seeks to solve]

In the above conventional technology, out of the margin of the reading system,
This takes into consideration the pattern peak shift on the time axis, that is, the phase margin.

However, the signal voltage that changes due to the waveform equalization circuit,
No consideration was given to the ratio of noise components caused by defects on the magnetic disk surface, the magnetic head, and even the readout circuit itself, that is, the S/N ratio.

Furthermore, among the margins of the readout system, the amplitude axis, that is, the slice level margin, was not considered as well.

In general, the factors that determine the phase margin include pattern peak shift caused by interference between adjacent bits, and S/N jitter caused by the ratio of the signal voltage of the limiter circuit to the noise voltage generated by the magnetic head, AMP, etc. As is clear from the prior art described above, by increasing the attenuation rate K, the tail of the waveform becomes slimmer, the mutual interference between adjacent bits becomes smaller, and the amount of pattern peak shift also becomes smaller. However, if the attenuation factor K is made too large, the pattern peak shifts in the opposite direction as shown in FIG. On the other hand, considering the relationship between the S/N jitter amount and the attenuation rate, the data pulse is output through a limiter circuit, and the limiter circuit inputs a differential waveform to detect the peak point. Therefore, as shown in FIG. 4, the degree of amplification increases depending on the frequency, and the limiter noise voltage also increases. As the attenuation rate K increases, the limiter noise voltage also increases, and therefore the relationship between the attenuation rate and the S/N jitter amount is as shown in FIG.

Next, considering the slice level margin system, the factors that determine the slice level margin are the signal voltage reduction rate determined by the signal frequency and the S
/N voltage reduction rate. Here, the signal voltage reduction rate is a signal voltage ratio that changes depending on the frequency, and the S/N voltage reduction rate is the ratio of the read signal voltage to the read noise voltage.

However, as described above, in the prior art, no consideration was given to optimizing the slice level margin due to these factors.

An object of the present invention is to improve the margins of both a phase margin system and a slice level margin system when configuring a readout circuit of a magnetic recording/reproducing apparatus.

°5 ゛・4 ・ [Means for solving the problem] In order to achieve the above-mentioned object, the present invention provides a waveform equalization circuit that equalizes the waveform of a read signal of a magnetic head, and a waveform equalization circuit that equalizes the waveform of a read signal of a magnetic head. A differentiation circuit that inputs a signal and converts it into a differential waveform, a limiter circuit that inputs this differential waveform and outputs a data pulse by detecting a peak point, a data discrimination circuit that identifies data from this data pulse, and In the readout circuit of a magnetic recording/reproducing device, which consists of a gate generation circuit that applies a timing signal for data discrimination to a data discrimination circuit, a waveform equalization circuit with different waveform equalization effects is installed in the stage before the limiter circuit and the gate generation circuit, respectively. A readout circuit for a magnetic recording/reproducing device is provided.

[Effect]

In the present invention, a waveform equalization circuit is provided before each of the limiter circuit and the gate generation circuit.

First, the improvement of the phase margin system using a limiter circuit provided with a waveform equalization circuit at the front stage will be explained.

As mentioned above, the pattern peak shift amount is waveform 6
・ Reduced by the attenuator of the equalization circuit, the attenuation factor K of the attenuator
It is desirable that the value is relatively large. However, as the attenuation rate K increases, the limiter noise voltage generated by the limiter circuit also increases. Therefore, by setting the attenuation rate K so that the ratio of the noise voltage to the signal voltage, that is, the sum of the S/N jitter amount determined by the S/N ratio and the pattern peak shift amount, is minimized, the phase margin can be optimized. becomes.

Next, an explanation will be given of improvement of the slice level margin system using a gate generation circuit provided with a waveform equalization circuit at the front stage.

First, consider the signal voltage reduction rate determined by the signal frequency. Output signal g for input signal f(1)
(t), that is, the signal voltage ratio R(t) changes depending on the attenuation rate K, and its characteristics are as shown in FIG. Then, the peak point of this characteristic becomes the optimum point of the signal voltage ratio. On the other hand, if we consider the S/N voltage reduction rate of the gate generation circuit, as shown in Figure 8, as the frequency increases, the voltage gain also increases, so the signal voltage also increases, and therefore the S/N
The N voltage reduction rate becomes smaller. This characteristic is shown in FIG. 9. Therefore, the optimum point of the slice level margin system can be obtained by setting the attenuation rate K so that the sum of the reciprocal of the signal voltage ratio and the S/N voltage reduction rate becomes the minimum.

As described above, it can be seen that the effects of the phase margin and slice level margin due to the waveform equalization circuit are different from each other, and the optimum points are also different.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. 1st
The figure is a block diagram showing a schematic configuration of a readout circuit according to the present invention. In FIG. 1, read signals from the magnetic head are applied to waveform equalization circuits 11 and 15, respectively. The signal whose waveform has been equalized by the waveform equalization circuit 11 is sent to the differentiation circuit 12.
After converting the peak position to the zero cross point of the differential waveform,
Low pass filter 13. The data passes through the limiter circuit 14 and is subjected to data discrimination by the data discrimination circuit 17. On the other hand, the signal whose waveform has been equalized by the waveform equalization circuit 15 passes through the low-pass filter 13 and then inputs to the gate generation circuit 16, where the signal obtained by the gate generation circuit 16 is 7 degrees.

The gate pulse is applied to the data discrimination circuit 17. These waveform equalization circuits 11 and 15 have different waveform equalization effects, and have different attenuation rates.

In the phase margin system using the waveform equalization circuit, the attenuation rate is set so that the sum of the S/N jitter amount and the pattern peak shift amount is minimized. When the sum of the pattern peak shift amount and the S/N jitter amount is plotted according to changes in the attenuation rate, the result is as shown in FIG. 6. From this Figure 6, in the phase margin system, the pattern peak shift amount and S
/N The sum of the jitter amounts is 7.4 ns, which is the minimum. As a result, in this example, the phase margin system could be improved by 2 to 3 nS.

On the other hand, in a slice level margin system using a waveform equalization circuit, the attenuation rate is set so that the sum of the reciprocal of the signal voltage ratio, that is, the 1/signal voltage ratio, and the voltage reduction rate due to the S/N of the gate generation circuit is minimized. .

Therefore, 17 signal voltage ratio and S/N・q of gate generation circuit
Figure 10 shows the sum of the voltage reduction rates due to bumps 8. plotted according to changes in the attenuation rate.

Therefore, as shown in FIG. 10, in the slice level margin system, when the attenuation rate is 0.55, the sum of the voltage reduction rate due to 1/signal voltage ratio and S/N becomes 40%, which is the minimum. As a result, in this example, the slice level margin system is 15 to 25
% could be improved.

〔Effect of the invention〕

According to the present invention, since waveform equalization circuits with different attenuation rates are provided before the limiter circuit and the gate generation circuit, both the phase margin and slice level margin are simultaneously improved for the read signal from the magnetic head. can be done.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a schematic configuration of a readout circuit of a magnetic recording device according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of a conventional readout circuit. FIG. 3 is a characteristic diagram showing the relationship between pattern peak shift amount and attenuation rate, and FIG. 4 is a limiter noise voltage °10. Figure 5 is a characteristic diagram showing the relationship between the amount of S/N jitter and attenuation rate, and Figure 6 is the sum of pattern peak shift amount and amount of S/N jitter and attenuation. Figure 7 is a characteristic diagram showing the relationship between signal voltage ratio R(t) and attenuation rate, and Figure 8 is a characteristic diagram showing the relationship between voltage gain and frequency depending on the value of attenuation rate. Figure 9 is a characteristic diagram showing the relationship between the voltage reduction rate (%) due to S/N and the attenuation rate, and Figure 10 is a characteristic diagram showing the relationship between the voltage reduction rate (%) due to S/N and the attenuation rate. FIG. 3 is a characteristic diagram showing the relationship between the sum and the attenuation rate. 1.11.15...Waveform equalization circuit, 2.12...Differentiating circuit, 3.13...Low pass filter, 4.14.
...Limiter circuit, 5.16...Gate generation circuit, 6
゜17...Data discrimination circuit.

Claims (1)

[Claims] 1. First and second waveform equalization circuits each have an attenuator and input read signals from the magnetic head and equalize the waveforms at a predetermined attenuation rate, and the first waveform equalization circuit performs waveform equalization. A differentiator circuit that converts the differential signal into a differential waveform, a limiter circuit that detects the peak point from the differential waveform from this differentiator circuit and outputs a data pulse, and identifies data from the data pulse obtained by this limiter circuit. a data discrimination circuit;
Reading of a magnetic recording device characterized by comprising a gate generation circuit inputting a signal whose waveform has been equalized by the second waveform equalization circuit and applying a timing signal for data discrimination to the data discrimination circuit. circuit.