JPH01176302A - Waveform equalizing circuit for recording and reproducing device - Google Patents

Waveform equalizing circuit for recording and reproducing device

Info

Publication number
JPH01176302A
JPH01176302A JP33318887A JP33318887A JPH01176302A JP H01176302 A JPH01176302 A JP H01176302A JP 33318887 A JP33318887 A JP 33318887A JP 33318887 A JP33318887 A JP 33318887A JP H01176302 A JPH01176302 A JP H01176302A
Authority
JP
Japan
Prior art keywords
amplifier
differential output
delay line
recording
output amplifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP33318887A
Other languages
Japanese (ja)
Inventor
Yasunori Orihara
折原 泰則
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP33318887A priority Critical patent/JPH01176302A/en
Publication of JPH01176302A publication Critical patent/JPH01176302A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To improve the SN ratio of a signal component and to reduce a cost by connecting the grounding edge of a delay line to a first output terminal of a differential output amplifier and connecting the signal input terminal of the delay line to a second output terminal of the differential output amplifier. CONSTITUTION:A grounding edge 5 of a delay line 1 is connected to the first output terminal 6 of a differential output amplifier 3 and a signal input terminal 7 of the delay line 1 is connected the second output terminal 8 of the differential output amplifier. Accordingly, even when the differential output amplifier 3 is not composed of an operational amplifier or a filter is not provided in a current voltage terminal, the in-phase noise component is not converted to a differential noise component and an in-phase component can be outputted to the amplifier of a next step as the in-phase component. Thus, the SN of the signal component can be improved and the cost can be reduced.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 したこの種波形等化回路に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to this type of waveform equalization circuit.

〔従来の技術〕[Conventional technology]

高密度磁気記録再生装置等にあっては、従来がら、デー
タの線密度を上げるために波形等化回路が使用されてい
る。
In high-density magnetic recording and reproducing devices, waveform equalization circuits have conventionally been used to increase the linear density of data.

しかして、波形等化回路には、一般に、第2図に示すよ
うな余弦等化回路が使用されており、遅延線1と特性イ
ンピーダンスが一致する抵抗2とを直列接続し、差動出
力増幅器3からの入射波と遅延線1からの反射波との合
成波形を、遅延線1の開放端4の出力波形から一定の比
で差し引くことにより、孤立波の裾領域を小さくして、
高域周波数成分を増加させるようにしている。
Generally, a cosine equalization circuit as shown in Fig. 2 is used as a waveform equalization circuit, in which a delay line 1 and a resistor 2 whose characteristic impedance matches each other are connected in series, and a differential output amplifier is connected. By subtracting the composite waveform of the incident wave from the delay line 3 and the reflected wave from the delay line 1 from the output waveform of the open end 4 of the delay line 1 at a constant ratio, the tail area of the solitary wave is reduced.
It is designed to increase high frequency components.

なお、この種波形等化回路に関する従来技術は、例えば
特開昭57−62426号および同58−039236
号公報に記載されている。
Note that prior art related to this type of waveform equalization circuit is disclosed in, for example, Japanese Patent Application Laid-open Nos. 57-62426 and 58-039236.
It is stated in the No.

〔発明が解決しようとする問題題〕[Problem that the invention seeks to solve]

しかし、前記従来技術にあっては、差動入力信号および
電源電圧からの同相成分雑音に対する配慮の点で欠ける
憾みがある。すなわち、第2図に示す波形等化回路によ
れば、増幅器3に入力される差動入力信号の同相成分と
、増幅器3の印加電源電圧からの雑音とが同相雑音成分
として出方され、また第2図においては、差動出力増幅
器3の片側の出力によって波形等化回路を構成している
ため、前記同相雑音成分は差動雑音成分となり、S/N
を低下させていた。
However, the conventional technique described above lacks consideration for common-mode component noise from the differential input signal and the power supply voltage. That is, according to the waveform equalization circuit shown in FIG. 2, the common-mode component of the differential input signal input to the amplifier 3 and the noise from the power supply voltage applied to the amplifier 3 are output as common-mode noise components. In FIG. 2, since the waveform equalization circuit is configured by the output of one side of the differential output amplifier 3, the common mode noise component becomes a differential noise component, and the S/N
was decreasing.

なお、前記したS/Nの低下防止対策としては、差動出
力増幅器3を同相成分を除去し易い演算増幅器で構成す
るか、あるいは電源電圧端子にフィルタを設けることが
考えられるが、いずれも同相信号成分を大幅に低減させ
る必要があり、高価なS/N低下防止対策回路とならざ
るを得ない難点があった。
Note that as a measure to prevent the S/N from decreasing as described above, it is possible to configure the differential output amplifier 3 with an operational amplifier that can easily remove the common-mode component, or to provide a filter on the power supply voltage terminal, but both methods are the same. It is necessary to significantly reduce the phase signal component, and there is a drawback that an expensive S/N reduction prevention circuit is required.

本発明は、以上の点を考慮してなされたものであって、
その目的とするところは、差動出力増幅器を演算増幅器
で構成したり、あるいは電源電圧端子にフィルタを設け
たりしなくても、差動出力増幅器の同相雑音成分が差動
雑音成分に変換されることなく、同相成分は同相成分と
して次段の増幅器に出力することのできる、信号成分の
S / N向上化は勿論のこと、経済的に安価な記録再
生装置の波形等化回路を提供しようとするものである。
The present invention has been made in consideration of the above points, and includes:
The purpose is to convert the common-mode noise component of the differential output amplifier into a differential noise component without configuring the differential output amplifier with an operational amplifier or installing a filter on the power supply voltage terminal. We aim to provide an economically inexpensive waveform equalization circuit for recording and reproducing devices, which not only improves the S/N of the signal component, but also allows the in-phase component to be output to the next stage amplifier as an in-phase component. It is something to do.

〔問題点を解決するための手段〕[Means for solving problems]

前記目的は、情報を記録する記録媒体と、記録媒体面上
に近接あるいは軟接触することにより情報の記録または
再生をおこなうヘッドと、ヘッドの微小信号を増幅する
増幅器と、増幅器内に少なくとも1段接続された差動出
力増幅器と、差動出力増幅器の後に接続され、ヘッド出
力波形を補正する遅延線を利用した波形等化回路とを備
える記録再生装置において、前記遅延線の接地端を差動
出力増幅器の第1の出力端子に接続し、遅延線の信号入
力端子を差動出力増幅器の第2の出力端子に接続するこ
とによって達成される。
The purpose is to provide a recording medium for recording information, a head for recording or reproducing information by coming into close or soft contact with the surface of the recording medium, an amplifier for amplifying minute signals from the head, and at least one stage in the amplifier. In a recording/reproducing apparatus comprising a differential output amplifier connected to the differential output amplifier and a waveform equalization circuit connected after the differential output amplifier and utilizing a delay line for correcting the head output waveform, the ground end of the delay line is connected to the differential output amplifier. This is achieved by connecting the signal input terminal of the delay line to the first output terminal of the output amplifier and the second output terminal of the differential output amplifier.

〔作用〕[Effect]

しかして、前記構成よりなる本発明によれば、遅延線の
接地端を差動出力端子に接続したことにより、後述の説
明からも明らかなように、差動出力増幅器の同相雑音成
分が差動出力成分に変換されることばなく、同相成分は
同相成分として次段の増幅器に出力される。
According to the present invention having the above configuration, by connecting the ground end of the delay line to the differential output terminal, the common mode noise component of the differential output amplifier is The in-phase component is output to the next stage amplifier as an in-phase component without being converted into an output component.

〔実施例〕〔Example〕

以下、本発明を、図面にもとづいて説明すると、第1図
は本発明に係る波形等化回路の一実施例を示す電気結線
図である。
Hereinafter, the present invention will be explained based on the drawings. FIG. 1 is an electrical wiring diagram showing one embodiment of a waveform equalization circuit according to the present invention.

第1図において、第2図に示す従来形波形等化回路と同
一符号は同一部分を示し、遅延線1の接地端5は、差動
出力増幅器3の第1の出力端子6に接続しされている。
In FIG. 1, the same symbols as those in the conventional waveform equalization circuit shown in FIG. 2 indicate the same parts, and the ground terminal 5 of the delay line 1 is connected to the first output terminal 6 of the differential output amplifier 3. ing.

また、遅延線1の入力端子7は、特性インピーダンスの
等しい抵抗2を介して差動出力増幅器3の第2出力端子
8に接続されており、次段の増幅器9の入力は、遅延線
1の開放端4と、遅延線1の入力端子7および差動出力
増幅器3の第1出力端子6間に接続された高抵抗の可変
抵抗器10のタップ端から入力される。
Further, the input terminal 7 of the delay line 1 is connected to the second output terminal 8 of the differential output amplifier 3 via a resistor 2 with equal characteristic impedance, and the input of the next stage amplifier 9 is connected to the second output terminal 8 of the differential output amplifier 3. The signal is input from the tap end of a high-resistance variable resistor 10 connected between the open end 4, the input terminal 7 of the delay line 1, and the first output terminal 6 of the differential output amplifier 3.

しかして、前記した第1図の余弦等化回路によれば、差
動出力増幅器3の出力に同相成分が含まれていても、遅
延線1の接地端5と入力端子7の差動電圧成分に同相成
分は含まれておらず、両端子とも同時に変動するだけで
あり、差動出力増幅器3の同相雑音成分は、差動雑音成
分に変換されることなく、同相成分のまま次段の増幅器
9に伝達され、したがって本発明によれば、信号成分の
S/N向上化は勿論のこと、信号成分の同相成分を除去
するための特別な回路、すなわち従来の高価なS/N低
下防止対策回路のように、差動出力増幅器を演算増幅器
で構成したり、あるいは電源電圧端子にフィルタを設け
たりする必要がなくなる。
According to the cosine equalization circuit shown in FIG. does not include a common-mode component, and only fluctuates at both terminals at the same time.The common-mode noise component of the differential output amplifier 3 is not converted into a differential noise component, but is passed through the next stage amplifier as a common-mode component. Therefore, according to the present invention, not only the S/N of the signal component can be improved, but also a special circuit for removing the in-phase component of the signal component, that is, the conventional expensive S/N reduction prevention measures can be used. Unlike other circuits, it is no longer necessary to configure the differential output amplifier with an operational amplifier or to provide a filter at the power supply voltage terminal.

なお、図示実施例においては、本発明を、余弦等化回路
を例にとって説明したが、これ以外にも、トランスバー
サル等化回路や微分形のトランスバーサル等化回路のよ
うに、遅延線を単数あるいは複数使用する等化回路であ
れば、前記実施例で説明したと同様の効果を得ることが
できる。
In the illustrated embodiment, the present invention has been explained by taking a cosine equalization circuit as an example. Alternatively, if a plurality of equalization circuits are used, it is possible to obtain the same effect as described in the above embodiment.

また、差動出力増幅器3は、各出力ごとに別々の増幅器
で構成するようにしても、前記実施例と同様の効果が得
られる。
Further, even if the differential output amplifier 3 is configured with a separate amplifier for each output, the same effect as in the embodiment described above can be obtained.

〔発明の効果〕〔Effect of the invention〕

本発明は以上のごときであり、本発明によれば、差動出
力増幅器を演算増幅器で構成したり、あるいは電源電圧
端子にフィルタを設けたりしなくても、差動出力増幅器
の同相雑音成分が差動雑音成分に変換されることなく、
同相成分は同相成分として次段の増幅器に出力すること
ができ、信号成分のS/N向上化は勿論のこと、経済的
に安価な記録再生装置の波形等化回路を得ることができ
る。
The present invention is as described above, and according to the present invention, the common mode noise component of the differential output amplifier can be reduced without configuring the differential output amplifier with an operational amplifier or without providing a filter on the power supply voltage terminal. without being converted into differential noise components.
The in-phase component can be output as an in-phase component to the next-stage amplifier, and not only can the S/N of the signal component be improved, but also an economically inexpensive waveform equalization circuit for a recording/reproducing device can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明に係る波形等化回路の一実施例を示す電
気結線図、第2図は従来形波形等化回路の電気結線図で
ある。 1・・・遅延線、2・・抵抗、3・・・差動出力増幅器
、9・・・増幅器、10・・・可変抵抗器。
FIG. 1 is an electrical wiring diagram showing an embodiment of a waveform equalization circuit according to the present invention, and FIG. 2 is an electrical wiring diagram of a conventional waveform equalization circuit. DESCRIPTION OF SYMBOLS 1... Delay line, 2... Resistor, 3... Differential output amplifier, 9... Amplifier, 10... Variable resistor.

Claims (1)

【特許請求の範囲】[Claims] 1、情報を記録する記録媒体と、記録媒体面上に近接あ
るいは軟接触することにより情報の記録または再生をお
こなうヘッドと、ヘッドの微小信号を増幅する増幅器と
、増幅器内に少なくとも1段接続された差動出力増幅器
と、差動出力増幅器の後に接続され、ヘッド出力波形を
補正する遅延線を利用した波形等化回路とを備える記録
再生装置において、前記遅延線の接地端を差動出力増幅
器の第1の出力端子に接続し、遅延線の信号入力端子を
差動出力増幅器の第2の出力端子に接続したことを特徴
とする記録再生装置の波形等化回路。
1. A recording medium for recording information, a head for recording or reproducing information by coming into close or soft contact with the surface of the recording medium, an amplifier for amplifying minute signals from the head, and at least one stage connected within the amplifier. In a recording/reproducing apparatus comprising a differential output amplifier and a waveform equalization circuit connected after the differential output amplifier and using a delay line for correcting a head output waveform, the ground end of the delay line is connected to the differential output amplifier. A waveform equalization circuit for a recording/reproducing apparatus, characterized in that the signal input terminal of the delay line is connected to the first output terminal of the differential output amplifier.
JP33318887A 1987-12-30 1987-12-30 Waveform equalizing circuit for recording and reproducing device Pending JPH01176302A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33318887A JPH01176302A (en) 1987-12-30 1987-12-30 Waveform equalizing circuit for recording and reproducing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33318887A JPH01176302A (en) 1987-12-30 1987-12-30 Waveform equalizing circuit for recording and reproducing device

Publications (1)

Publication Number Publication Date
JPH01176302A true JPH01176302A (en) 1989-07-12

Family

ID=18263289

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33318887A Pending JPH01176302A (en) 1987-12-30 1987-12-30 Waveform equalizing circuit for recording and reproducing device

Country Status (1)

Country Link
JP (1) JPH01176302A (en)

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