JPH0548522B2 - - Google Patents

Info

Publication number
JPH0548522B2
JPH0548522B2 JP22103784A JP22103784A JPH0548522B2 JP H0548522 B2 JPH0548522 B2 JP H0548522B2 JP 22103784 A JP22103784 A JP 22103784A JP 22103784 A JP22103784 A JP 22103784A JP H0548522 B2 JPH0548522 B2 JP H0548522B2
Authority
JP
Japan
Prior art keywords
signal
waveform
input
delay circuit
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP22103784A
Other languages
Japanese (ja)
Other versions
JPS6199906A (en
Inventor
Hiroshi Muto
Takashi Aikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP22103784A priority Critical patent/JPS6199906A/en
Publication of JPS6199906A publication Critical patent/JPS6199906A/en
Publication of JPH0548522B2 publication Critical patent/JPH0548522B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B5/00Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor
    • G11B5/02Recording, reproducing, or erasing methods; Read, write or erase circuits therefor
    • G11B5/027Analogue recording
    • G11B5/035Equalising
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10Digital recording or reproducing
    • G11B20/10009Improvement or modification of read or write signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Digital Magnetic Recording (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、磁気装置の薄膜磁気ヘツドによる再
生波形の波形補正に用いられる波形等価回路に関
するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a waveform equivalent circuit used for waveform correction of a reproduced waveform by a thin film magnetic head of a magnetic device.

磁気装置は磁気ヘツドにより磁気記録媒体に情
報の記録と、記録された情報の再生を行う。近
年、記録の高密度化と再生情報の品質向上を得る
ため、磁気ヘツドに薄膜磁気ヘツドが多く用いら
れている。この薄膜磁気ヘツドによる再生におい
て、特に、記録磁気媒体の磁化反転位置の再生信
号である孤立波再生波形の立上がりおよび立下が
り点に薄膜磁気ヘツド特有の負のピークを発生す
る。
A magnetic device records information on a magnetic recording medium and reproduces the recorded information using a magnetic head. In recent years, thin film magnetic heads have been widely used in order to achieve higher recording density and improved quality of reproduced information. During reproduction by this thin film magnetic head, negative peaks peculiar to the thin film magnetic head occur particularly at the rising and falling points of the solitary wave reproduction waveform, which is the reproduction signal at the magnetization reversal position of the recording magnetic medium.

この負のピークは記録データに対応しない信号
であり、エラーレート特性において、振幅マージ
ンが減少し、信号再生系の信頼性を著しく低下さ
せる。そこで、記録再生波形を損なうことなく負
のピークを打ち消し、かつ、半値幅を狭める波形
等化回路が必要とされている。
This negative peak is a signal that does not correspond to recorded data, and in error rate characteristics, the amplitude margin decreases, significantly lowering the reliability of the signal reproduction system. Therefore, there is a need for a waveform equalization circuit that cancels negative peaks and narrows the half-width without damaging the recording/reproduction waveform.

〔従来の技術〕[Conventional technology]

第5図は従来の波形等化回路のブロツク図を示
し、第6図に従来の波形等化回路の動作を説明す
るための信号波形図を示している。
FIG. 5 shows a block diagram of a conventional waveform equalization circuit, and FIG. 6 shows a signal waveform diagram for explaining the operation of the conventional waveform equalization circuit.

すなわち、第5図において、第6図の入力孤立
波再生信号A1は、入力を抵抗R0で終端してある
遅延量τの遅延回路1によりτだけ遅れた信号A
とされた後、終端抵抗R0に比例して十分大きい
入力インピーダンスを持つた加算器2の+端に入
力される。このとき、インピーダンスの不整合に
より、信号Aは反射して再び遅延回路1によりτ
だけ遅れ、第6図Bの波形とされた後、減衰器3
により所定量減衰し、遅延回路1の出力信号とは
逆極性の第6図Cの信号となり、加算器2の−端
に入力される。加算器2は信号Aと信号Cとを加
算して信号Aの立上がりおよび立下がり個所を打
ち消すことにより第6図Dに示すような尖鋭な信
号を得る。
That is, in FIG. 5, the input solitary wave reproduction signal A1 of FIG. 6 is converted into a signal A delayed by τ by a delay circuit 1 whose input is terminated with a resistor R0 and has a delay amount τ.
After that, it is input to the + end of the adder 2, which has a sufficiently large input impedance in proportion to the terminating resistor R0. At this time, due to the impedance mismatch, the signal A is reflected and sent back to the delay circuit 1 by τ
After the waveform shown in Fig. 6B is delayed, the attenuator 3
The signal is attenuated by a predetermined amount and becomes the signal shown in FIG. Adder 2 adds signal A and signal C and cancels the rising and falling points of signal A to obtain a sharp signal as shown in FIG. 6D.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記の波形等化回路は、従来のフエライトヘツ
ドによる孤立波形を補正する回路例を示したが、
薄膜磁気ヘツドの再生信号に同様の波形等化を行
なつた場合には、孤立波再生波形における独特の
負のピーク(第3図の再生波形図T2参照)のた
め、ビツト間隔の広い部分で記録データに対応し
ない負のピークが生じる。このため、エラーレー
ト特性において、特に振幅マージンが減少し、信
号再生系の信頼度を著しく低下させるという問題
がある。
The above waveform equalization circuit is an example of a circuit that corrects an isolated waveform caused by a conventional ferrite head.
When similar waveform equalization is applied to the reproduced signal of a thin-film magnetic head, due to the unique negative peak in the solitary wave reproduced waveform (see reproduced waveform diagram T2 in Figure 3), the reproduction signal is A negative peak occurs that does not correspond to the recorded data. For this reason, there is a problem in error rate characteristics, particularly in that the amplitude margin is reduced and the reliability of the signal reproduction system is significantly reduced.

そこで、薄膜磁気ヘツド特有の孤立波再生波形
の負のピークを除去する機能と、信号の半値幅を
狭めて信号を尖鋭化する機能を持つた、薄膜磁気
ヘツドの再生信号に適した信号が得られる波形等
化回路が必要となる。
Therefore, by having the function of removing the negative peak of the solitary wave reproduction waveform peculiar to thin-film magnetic heads and the function of sharpening the signal by narrowing the half-width of the signal, a signal suitable for reproduction signals of thin-film magnetic heads can be obtained. A waveform equalization circuit is required.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、上記問題点を解消した波形等化回路
を提供するもので、その手段は、波形等化される
信号が入力すると入力端を所定の抵抗値で終端さ
れた第1の遅延回路と、該第1の遅延回路の異な
つた遅延量を有し、かつ、それと直列に接続され
た第2の遅延回路と、前記第2の遅延回路と出力
端を第1の入力端に接続した前記終端抵抗と不整
合の加算器と、入力の一端に接続するとともに、
前記第1の遅延回路の入力端にその入力端を接続
し、かつ、出力端を前記加算器の第2の入力端に
接続した第1の減衰器と、前記第1の遅延回路の
出力端にその入力端を接続し、かつ、出力端を前
記加算器の第3の入力端に接続した第2の減衰器
とからなる波形等化回路によつてなされる。
The present invention provides a waveform equalization circuit that solves the above-mentioned problems, and the means thereof includes, when a signal to be waveform equalized is input, a first delay circuit whose input end is terminated with a predetermined resistance value. , a second delay circuit having a different delay amount from the first delay circuit and connected in series thereto, and the second delay circuit having an output terminal connected to the first input terminal. Connect the terminating resistor and mismatched adder to one end of the input, and
a first attenuator whose input end is connected to the input end of the first delay circuit and whose output end is connected to the second input end of the adder; and an output end of the first delay circuit. and a second attenuator whose input end is connected to the third input end of the adder, and a second attenuator whose output end is connected to the third input end of the adder.

〔作用〕[Effect]

上記波形等化回路は、遅延量の異なつた2つの
遅延回路を直列に接続し、上記直列遅延回路の出
力端を直列遅延回路の入力端にの終端インピーダ
ンスと不整合のインピーダンスを持つた加算器に
おける一方の入力端に接続してインピーダンスの
不整合による反射を利用し、上記2つの遅延回路
を通過することによつて得られる入力波の遅延信
号と、反射波の遅延信号とからなる5種類の信号
を作成し、入力信号の負のピーク形状に対応して
前記作成された5種類の信号レベルを減衰器で所
定量それぞれ減衰し、加算器で加算することによ
つて薄膜磁気ヘツド特有の孤立波における負のピ
ークを打ち消し、かつ、波形の半値幅を狭めてい
る。
The waveform equalization circuit is an adder in which two delay circuits with different amounts of delay are connected in series, and the output terminal of the series delay circuit has an impedance mismatched with the terminal impedance of the input terminal of the series delay circuit. There are five types of delayed signals: an input wave delay signal obtained by connecting to one input terminal of the The five types of signal levels created above are attenuated by a predetermined amount in an attenuator in accordance with the negative peak shape of the input signal, and added in an adder to obtain the characteristics unique to thin-film magnetic heads. It cancels out the negative peak in the solitary wave and narrows the half-width of the waveform.

〔実施例〕〔Example〕

以下、図面を参照して本発明の実施例を詳細に
説明する。
Embodiments of the present invention will be described in detail below with reference to the drawings.

第1図は本発明の一実施例の波形等化回路のブ
ロツク図、第2図はこの実施例の動作を説明する
ための信号波形図、第3図は薄膜磁気ヘツドの再
生信号波形図を示している。
FIG. 1 is a block diagram of a waveform equalization circuit according to an embodiment of the present invention, FIG. 2 is a signal waveform diagram for explaining the operation of this embodiment, and FIG. 3 is a reproduction signal waveform diagram of a thin film magnetic head. It shows.

第1図のブロツク図に示すように本実施例の波
形等化回路は、磁気ヘツドの再生信号が入力され
る入力端をインピーダンスR0の抵抗体4で終端
した遅延量τ2を持つ第1の遅延回路5と、第1の
遅延回路5と異なつた遅延量τ1を持つて直列に接
続された第2の遅延回路6と、前記終端抵抗体4
と不整合の入力インピーダンスを有する第1の入
力端を前記第2の遅延回路6の出力端に接続した
加算器9と、第1の遅延回路の入力端および出力
端に接続され、それらの接続点における信号、す
なわち前記再生信号およびその遅延信号を別々に
所定量減衰して加算器9の第2および第3の入力
端に出力する第1および第2の減衰器7,8とよ
り構成されている。
As shown in the block diagram of FIG. 1, the waveform equalization circuit of this embodiment has a first delay having a delay amount τ2, in which the input terminal to which the reproduced signal of the magnetic head is input is terminated with a resistor 4 having an impedance R0. a circuit 5, a second delay circuit 6 connected in series with a delay amount τ1 different from that of the first delay circuit 5, and the terminating resistor 4.
an adder 9 whose first input terminal having an input impedance mismatched with the output terminal of the second delay circuit 6 is connected to the input terminal and the output terminal of the first delay circuit; The adder 9 includes first and second attenuators 7 and 8 that separately attenuate the signal at the point, that is, the reproduced signal and its delayed signal, by a predetermined amount and output the attenuated signals to the second and third input terminals of the adder 9. ing.

その動作を第2図の信号波形図を参照して説明
する。すなわち、第2の遅延回路6の出力が開放
端とみなせることから、ここで信号が反転し、終
端抵抗体4まで伝搬し、終端される。これによ
り、第1の減衰器7には第2図Eに示す波形等価
回路の入力(ヘツドの再生信号)に対して遅延量
が0の信号と、2(τ1+τ2)の2種類の信号が加
わり、第2の減衰器8には第2図Fに示す波形等
化回路の入力に対して遅延量がτ2の信号と、2τ1
+τ2の2種類の信号が加わる。加算器9には、前
記遅延回路6の出力信号(第2図G)と、減衰器
7および8により再生信号の負のピークに対応し
て所定量減衰された4種類と合計5種類のそれぞ
れ時間差を持つた信号が入力し、加算される。
The operation will be explained with reference to the signal waveform diagram in FIG. That is, since the output of the second delay circuit 6 can be regarded as an open end, the signal is inverted here, propagates to the terminating resistor 4, and is terminated. As a result, two types of signals are added to the first attenuator 7: a signal with a delay amount of 0 and a signal with a delay amount of 2 (τ1 + τ2) with respect to the input of the waveform equivalent circuit (head reproduction signal) shown in FIG. 2E. , the second attenuator 8 receives a signal whose delay amount is τ2 with respect to the input of the waveform equalization circuit shown in FIG.
Two types of signals +τ2 are added. The adder 9 receives the output signal of the delay circuit 6 (FIG. 2G) and four types attenuated by a predetermined amount corresponding to the negative peak of the reproduced signal by the attenuators 7 and 8, for a total of five types. Signals with time differences are input and added.

このとき、遅延回路5および6の遅延量τ1およ
びτ2を第3図に示す薄膜磁気ヘツドによる孤立再
生波形に対して、(T1/2)≦τ1≦(3T1/2)お
よび、T2−(T1/2)≦τ1+τ2≦T2+(T1/2)
を満たすように設定することによつて、薄膜磁気
ヘツド特有の孤立波におけるい負のピークを打ち
消し、かつ、再生信号の半値幅を狭めることがで
きる。また、第1の減衰器7の減衰比K2は、孤
立波形の正のピーク高さと負のピーク高さとの比
と同程度とし、第2の減衰器8の減衰比K1は再
生信号中の隣接ビツト間の波形干渉が十分小さく
なる値に設定すればよい。なお、本発明の実施例
での説明では2つの遅延回路を使用しているが、
中間タツプを有する1つの遅延回路を用いれば、
さらに使用部品点数を減少し、回路が簡略化でき
くことは言うまでもない。
At this time, the delay amounts τ1 and τ2 of the delay circuits 5 and 6 are set to (T1/2)≦τ1≦(3T1/2) and T2−(T1 /2)≦τ1+τ2≦T2+(T1/2)
By setting so as to satisfy the above conditions, it is possible to cancel out negative peaks in solitary waves peculiar to thin-film magnetic heads, and to narrow the half-width of the reproduced signal. Further, the attenuation ratio K2 of the first attenuator 7 is approximately the same as the ratio of the positive peak height to the negative peak height of the isolated waveform, and the attenuation ratio K1 of the second attenuator 8 is set to the same level as the ratio of the positive peak height to the negative peak height of the isolated waveform. It is sufficient to set the value to a value that makes waveform interference between bits sufficiently small. In addition, although two delay circuits are used in the explanation of the embodiment of the present invention,
Using one delay circuit with an intermediate tap, we get
Furthermore, it goes without saying that the number of parts used can be reduced and the circuit can be simplified.

第4図は本発明の他の実施例の波形等化回路の
ブロツク図を示している。
FIG. 4 shows a block diagram of a waveform equalization circuit according to another embodiment of the present invention.

第1図と異なるのは、円板状の記録媒体上のヘ
ツドの半径方向と位置精度により遅延回路11,
12の遅延量および減衰器13,14の減衰比な
どの等化条件を設定する等化条件設定回路10を
備えた点である。この実施例では、円板状記録媒
体の半径方向位置による周速の変化に対応した最
適等化条件が設定できるので、ヘツドの半径方向
位置のすべてにおいて良質の信号を得ることがで
き、装置としての信頼性を著るしく向上させるこ
とができる。
The difference from FIG. 1 is that the delay circuit 11,
12 and the attenuation ratio of attenuators 13 and 14. In this embodiment, it is possible to set optimal equalization conditions that correspond to changes in circumferential speed depending on the radial position of the disc-shaped recording medium, so it is possible to obtain high-quality signals at all radial positions of the head, and the device is can significantly improve reliability.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明によれば、比較的簡
単な回路構成により、薄膜磁気ヘツド特有の孤立
波再生波形における負のピークを除去することが
でき、かつ、波形の半値幅を狭めることができ、
薄膜磁気ヘツド信号再生系の信頼性の向上に大き
な効果がある。
As explained above, according to the present invention, with a relatively simple circuit configuration, it is possible to remove the negative peak in the solitary wave reproduction waveform peculiar to a thin-film magnetic head, and to narrow the half-width of the waveform. ,
This has a great effect on improving the reliability of the thin film magnetic head signal reproduction system.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図および第2図は本発明の一実施例の波形
等化回路のブロツク図と同回路の動作を説明する
ための信号波形図、第3図は薄膜磁気ヘツドの再
生信号波形図、第4図は本発明の他の実施例の波
形等化回路のブロツク図、第5図は従来の波形等
化回路のブロツク図を示し、第6図は従来の波形
等化回路の動作を説明するための信号波形図であ
る。 図において、1,11,12は遅延回路、2は
加算器、3,13,14は減衰器、4は入力終端
抵抗体、5は第1の遅延回路、6は第2の遅延回
路、7は第1の減衰器、8は第2の減衰器、9は
加算器、10は等化条件設定回路をそれぞれ示し
ている。
1 and 2 are a block diagram of a waveform equalization circuit according to an embodiment of the present invention and a signal waveform diagram for explaining the operation of the circuit. FIG. 3 is a reproduction signal waveform diagram of a thin film magnetic head, and FIG. FIG. 4 shows a block diagram of a waveform equalization circuit according to another embodiment of the present invention, FIG. 5 shows a block diagram of a conventional waveform equalization circuit, and FIG. 6 explains the operation of the conventional waveform equalization circuit. FIG. In the figure, 1, 11, 12 are delay circuits, 2 is an adder, 3, 13, 14 are attenuators, 4 is an input termination resistor, 5 is a first delay circuit, 6 is a second delay circuit, 7 8 represents a first attenuator, 8 represents a second attenuator, 9 represents an adder, and 10 represents an equalization condition setting circuit.

Claims (1)

【特許請求の範囲】[Claims] 1 波形等化される信号が入力する入力端を所定
の抵抗値で終端された第1の遅延回路と、該第1
の遅延回路の異なつた遅延量を有し、かつ、それ
と直列に接続された第2の遅延回路と、前記第2
の遅延回路の出力端を第1の入力端に接続した前
記終端抵抗と不整合の加算器と、入力の一端に接
続するとともに、前記第1の遅延回路の入力端に
その入力端を接続し、かつ、出力端を前記加算器
の第2の入力端に接続した第1の減衰器と、前記
第1の遅延回路の出力端にその入力端を接続し、
かつ、出力端を前記加算器の第3の入力端に接続
した第2の減衰器とからなることを特徴とする波
形等化回路。
1. A first delay circuit whose input terminal, into which a signal to be waveform-equalized, is input is terminated with a predetermined resistance value;
a second delay circuit having a different delay amount and connected in series with the delay circuit;
an adder that is mismatched with the terminating resistor, the output end of which is connected to the first input end of the delay circuit; , and a first attenuator whose output end is connected to the second input end of the adder, and whose input end is connected to the output end of the first delay circuit,
and a second attenuator whose output terminal is connected to the third input terminal of the adder.
JP22103784A 1984-10-19 1984-10-19 Waveform equalizing circuit Granted JPS6199906A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22103784A JPS6199906A (en) 1984-10-19 1984-10-19 Waveform equalizing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22103784A JPS6199906A (en) 1984-10-19 1984-10-19 Waveform equalizing circuit

Publications (2)

Publication Number Publication Date
JPS6199906A JPS6199906A (en) 1986-05-19
JPH0548522B2 true JPH0548522B2 (en) 1993-07-21

Family

ID=16760493

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22103784A Granted JPS6199906A (en) 1984-10-19 1984-10-19 Waveform equalizing circuit

Country Status (1)

Country Link
JP (1) JPS6199906A (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2557529B2 (en) * 1989-08-17 1996-11-27 富士通株式会社 Magnetic recording / reproducing circuit
DE69022763T2 (en) * 1989-03-31 1996-03-28 Fujitsu Ltd Recording and playback circuit for data.
US5337198A (en) * 1990-11-30 1994-08-09 Hitachi, Ltd. Digital magnetic writing and reading apparatus
DE69227309T2 (en) * 1992-01-10 1999-03-11 Fujitsu Ltd., Kawasaki, Kanagawa CIRCUIT FOR EQUALIZING THE WAVEFORM OF A SIGNAL PLAYED OUT BY A THIN FILM MAGNETIC HEAD
JP3212415B2 (en) * 1993-04-26 2001-09-25 株式会社リコー Control method of optical recording device

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